公开(公告)号：US10278302B2

公开(公告)日：2019-04-30

申请号：US14757972

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Anne M. Sepic ,  Zhen Zhou ,  Evan M. Fledell

IPC: H05K7/10 ,  G01R1/04 ,  H01R12/70 ,  H01R12/50 ,  H05K3/30 ,  H05K1/18

Abstract: Techniques and mechanisms for providing socket connection to a substrate. In an embodiment, a socket device includes a first socket body portion that is to provide for signal exchanges as part of a socket connector including the first socket body portion and a second socket body portion. The first socket body portion and the second socket body portion comprise respective zones, wherein, of the two zones, only one such zone has a first electro-mechanical characteristic. The first electro-mechanical characteristic is selected from the group consisting of an interconnect dimension, an interconnect material, an interconnect structure, a socket body material, and a shielding structure. In another embodiment, modular socket sub-assemblies each comprise a respective one of the first zone and the second zone.

公开(公告)号：US10074919B1

公开(公告)日：2018-09-11

申请号：US15625149

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Zhen Zhou ,  Daqiao Du ,  Anne M. Sepic ,  Kai Xiao

IPC: H01R12/00 ,  H01R12/71 ,  H01R12/75 ,  H01R43/20 ,  H05K1/09 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00

CPC classification number: H01R12/714 ,  H01R12/75 ,  H01R43/205 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09545 ,  H05K2201/10265 ,  H05K2201/10909 ,  H05K2203/06 ,  H05K2203/162

Abstract: Embodiments of the present disclosure may relate to a printed circuit board (PCB) that includes a first outer layer and a second outer layer opposite the first outer layer. The PCB may further include a routing layer between the first outer layer and the second outer layer, and an interconnect positioned within the first outer layer and coupled with the routing layer. The interconnect may include a contact within an opening in the first outer layer, wherein the contact is within a plane defined by an outer surface of the first outer layer. The interconnect may further include a plated via directly coupled with the contact and the routing layer. Other embodiments may be described or claimed.