公开(公告)号：US12196807B2

公开(公告)日：2025-01-14

申请号：US17133659

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Zhen Zhou ,  Renzhi Liu ,  Jong-Ru Guo ,  Kenneth P. Foust ,  Jason A. Mix ,  Kai Xiao ,  Zuoguo Wu ,  Daqiao Du

IPC: G01R31/302 ,  G01R31/28 ,  G01R31/303 ,  H01P3/08 ,  H01Q9/16 ,  H04B5/48

Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

公开(公告)号：US20230112996A1

公开(公告)日：2023-04-13

申请号：US17907261

申请日：2020-04-30

Applicant: Intel Corporation

Inventor： BIN YANG ,  Jia Bao ,  Mohammad Haghighat ,  Fei Li ,  Zhiwei Li ,  Mingqui Sun ,  Tao Xu ,  Zhen Zhou

IPC: G06F8/41 ,  G06F8/77

Abstract: Systems, apparatuses and methods may be associated with a first computing device and provide for identifying performance metrics. The performance metrics are associated with execution of a first function on at least one second computing device. The systems, apparatuses and methods aggregate the performance metrics to generate aggregated performance metrics, determine that the aggregated performance metrics meet a threshold and compile code associated with the first function in response to the aggregated performance metrics being determined to meet the threshold.

公开(公告)号：US11489257B2

公开(公告)日：2022-11-01

申请号：US17335301

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Ali Sadri ,  Debabani Choudhury ,  Bradley Jackson ,  Shengbo Xu ,  Tae Young Yang ,  Zhen Zhou ,  Cheng-Yuan Chin

IPC: H01Q3/44 ,  H01Q19/06 ,  H01Q21/06

Abstract: A lens antenna system is disclosed. The lens antenna system comprises a hybrid focal source antenna circuit configured to generate a source antenna beam for integration with different lens structures. In some embodiments, the hybrid focal source antenna circuit comprises a set of antenna elements coupled to one another. In some embodiments, the set of antenna elements comprises a first antenna element configured to be excited in a first spherical mode; and a second antenna element configured to be excited in a second, different, spherical mode. In some embodiments, the first spherical mode and the second spherical mode are co-polarized. In some embodiments, the lens antenna system further comprises a lens configured to shape the source antenna beam associated with the hybrid focal source antenna circuit, in order to provide an output antenna beam.

公开(公告)号：US20210351535A1

公开(公告)日：2021-11-11

申请号：US17384091

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Ismael Franco Núñez ,  Daqiao Du ,  Zhen Zhou ,  Gordon P. Melz

IPC: H01R13/24 ,  H01R12/71 ,  H01R12/70

Abstract: In one embodiment, an interconnect apparatus (e.g., an interposer apparatus) includes a plurality of interconnect probes that each include a wave spring structure that includes a plurality of stacked wave spring discs. The wave spring discs may be formed in a sinusoidal wave form shape, or in another wave form shape.

公开(公告)号：US10831216B2

公开(公告)日：2020-11-10

申请号：US15573313

申请日：2016-12-22

Applicant: INTEL CORPORATION

Inventor： Ke Han ,  Zhen Zhou ,  Guangyu Ren ,  Zhiqiang Qin

IPC: G05D1/10 ,  B64C39/02 ,  G01C5/06 ,  G01S5/02 ,  G01S5/06 ,  G01S11/06 ,  G01S19/46

Abstract: Apparatus, method and storage medium associated with UAV position estimation are disclosed herein. In embodiments, an UAV may comprise a transmitter-receiver arrangement to transmit and receive communication signals, including receipt of absolute positioning system (APS) signals from one or more APS sensors, and wireless signals from one or more proximately located other UAVs; one or more motors or engines to provide propulsive force for the UAV; and a flight controller coupled to the transmitter-receiver arrangement and the one or more motors or engines to control at least the one or more motors or engines to provide propulsive force to navigate the UAV, based at least in part on the APS and relative positioning signals. Other embodiments may be disclosed or claimed.

公开(公告)号：US20200312031A1

公开(公告)日：2020-10-01

申请号：US16650298

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Chao Huang ,  Zhen Zhou ,  Manju Sabharwal

IPC: G06T19/00 ,  G06F3/01

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to map a virtual environment to a physical environment using a weighted linear mapping technique. Example methods disclosed herein include accessing dimensional data corresponding to the virtual environment. Disclosed example methods further include determining areas of relative importance in the virtual environment. Disclosed example methods also include accessing dimensional data corresponding to the physical environment and generating a mapped environment based on the dimensional data corresponding to the virtual environment, the dimensional data corresponding to the physical environment, and the areas of relative importance.

公开(公告)号：US20200257628A1

公开(公告)日：2020-08-13

申请号：US16649713

申请日：2017-11-22

Applicant: INTEL CORPORATION

Inventor： Liang Fang ,  Zhen Zhou

IPC: G06F12/0862 ,  G06F12/123 ,  G06F9/30 ,  G06F9/4401 ,  G06F16/17 ,  G06F16/16

Abstract: Techniques are provided for the scheduling of file pre-fetches from a file system into a cache memory, to reduce subsequent latency associated with future accesses to those files. A methodology implementing the techniques according to an embodiment includes monitoring accesses to files of the file system (e.g., file open and file read operations) and maintaining a record for each of the accessed files. The record includes an identifier of the file, the number of accesses of the file, and the number of cache memory misses associated with those accesses. The method also includes storing the record into a file access history database (FAHD). The method further includes generating, in response to an Operating System (OS) shutdown, a frequently used file list (FUFL) based on the FAHD. The method further includes pre-fetching files identified by a selected subset of the FUFL to the cache memory during an OS boot.

公开(公告)号：US20190146699A1

公开(公告)日：2019-05-16

申请号：US16300143

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Padmashree K. Apparao ,  Zhen Zhou

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for compressed virtual memory (CVM) management using CVM arbitration. CVM arbitration may monitor CVM utilization, tune CVM and update CVM settings that may be enabled upon reboot of a system and/or apparatus. The CVM arbitration may improve memory management, thereby improving system performance and user experience.

公开(公告)号：US10074919B1

公开(公告)日：2018-09-11

申请号：US15625149

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Zhen Zhou ,  Daqiao Du ,  Anne M. Sepic ,  Kai Xiao

IPC: H01R12/00 ,  H01R12/71 ,  H01R12/75 ,  H01R43/20 ,  H05K1/09 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00

CPC classification number: H01R12/714 ,  H01R12/75 ,  H01R43/205 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09545 ,  H05K2201/10265 ,  H05K2201/10909 ,  H05K2203/06 ,  H05K2203/162

Abstract: Embodiments of the present disclosure may relate to a printed circuit board (PCB) that includes a first outer layer and a second outer layer opposite the first outer layer. The PCB may further include a routing layer between the first outer layer and the second outer layer, and an interconnect positioned within the first outer layer and coupled with the routing layer. The interconnect may include a contact within an opening in the first outer layer, wherein the contact is within a plane defined by an outer surface of the first outer layer. The interconnect may further include a plated via directly coupled with the contact and the routing layer. Other embodiments may be described or claimed.

公开(公告)号：US20220374158A1

公开(公告)日：2022-11-24

申请号：US17764113

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Bin Yang ,  Chao Xie ,  Dong-Yuan Chen ,  Jia Bao ,  Mingqiu Sun ,  Mohammad R. Haghighat ,  Qiming Shi ,  Zhen Zhou

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide technology for managing a runtime computing environment having tiered object memory placement that assigns a hotness score to an object having an object type based on an invocation count of objects referenced by a hot method, allocates a newly-created object to one of a hot object heap, said hot object heap assigned to store hot objects in a first memory tier, or a cold object heap, said cold object heap assigned to store cold objects in a second memory tier, based on the hotness score associated with the object type for the newly-created object, and migrates a plurality of objects between the hot object heap and the cold object heap based on a hotness score associated with each object. The technology may also operate the object migration in an execution thread independent of an execution thread for the object allocation.