公开(公告)号：US20040016996A1

公开(公告)日：2004-01-29

申请号：US10206246

申请日：2002-07-26

Applicant: INTEL CORPORATION

Inventor： John Tang

IPC: H01L023/02

CPC classification number: H01L23/15 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2924/15174 ,  H01L2924/19106

Abstract: A semiconductor device is provided that includes one or more ceramic material layers and one or more low dielectric constant (low-K) epoxy layers on top to be electrically coupled to an integrated circuit device, such as a chip die. The resulting ceramic/organic hybrid substrate takes advantage of the thin low-cost, low-K epoxy layer, by routing the dense circuitry from the chip die to the ceramic material layer. In addition, the use of low-K epoxy layer may reduce the number of ceramic material layers required to about three layers, thus significantly reducing the cost of the substrate. Low-K epoxy material layer may be laminated onto the ceramic material layer to reduce throughput time and cost. The ceramic/organic hybrid substrate may also take advantage of the properties of ceramic materials, which have a much more rigid structure than organic materials and a low CTE (coefficient of thermal expansion) that works well with ultra low-K chip dies. The ceramic/organic hybrid substrate also may make possible the fabrication of a bottom cavity package for capacitors placement.

Abstract translation: 提供一种半导体器件，其包括一个或多个陶瓷材料层和顶部上的一个或多个低介电常数（低K）环氧树脂层，以电耦合到诸如芯片裸片的集成电路器件。 所得到的陶瓷/有机混合基板利用薄的低成本，低K环氧树脂层，通过将密集电路从芯片芯片路由到陶瓷材料层。 此外，使用低K环氧树脂层可以减少约三层所需的陶瓷材料层的数量，从而显着降低基板的成本。 低K环氧材料层可以层压在陶瓷材料层上以减少生产时间和成本。 陶瓷/有机混合基板还可以利用具有比有机材料更刚性结构的陶瓷材料的特性以及与超低K芯片裸片工作良好的低CTE（热膨胀系数）的优点。 陶瓷/有机混合基板还可以制造用于电容器放置的底部空腔封装。

公开(公告)号：US20030045083A1

公开(公告)日：2003-03-06

申请号：US09946749

申请日：2001-09-05

Applicant: Intel Corporation

Inventor： Steven Towle ,  John Tang ,  John S. Cuendet ,  Henning Braunisch ,  Thomas S. Dory

IPC: H01L021/44

CPC classification number: H01L23/5389 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15173 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

Abstract translation: 低成本微电子电路封装包括在微电子管芯上方的单个堆积金属化层。 使用例如封装材料将至少一个管芯固定在封装芯内。 然后在模具/芯组件上构建单个金属化层。 金属化层包括许多具有允许微电子器件直接安装到外部电路板的间距的着陆焊盘。 在一个实施例中，金属化层包括在该层的外围区域内的多个信号着陆焊盘以及朝向该层的中心区域的至少一个电源着陆焊盘和一个接地焊盘。

公开(公告)号：US20020158335A1

公开(公告)日：2002-10-31

申请号：US09845896

申请日：2001-04-30

Applicant: Intel Corporation

Inventor： Steven Towle ,  John Tang ,  Gilroy Vandentop

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/24 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H01L2924/3011 ,  Y10S257/924

Abstract: A low cost technique for packaging microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuit using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core assembly before lamination of the interposer.

Abstract translation: 用于封装微电子电路芯片的低成本技术将芯片固定在封装芯的开口内。 然后在模具/芯组件上形成至少一个金属堆积层，并且将栅格阵列插入单元层叠到堆积层上。 然后可以使用多种安装技术（例如，球栅阵列（BGA），焊盘网格阵列（LGA），引脚网格阵列（PGA），表面贴装技术（SMT）等）中的任何一种将栅格阵列插入单元安装在外部电路内 ）和/或其他）。 在一个实施例中，在层压插入件之前，在模具/芯组件上形成单个堆积层。