公开(公告)号：US20030045083A1

公开(公告)日：2003-03-06

申请号：US09946749

申请日：2001-09-05

Applicant: Intel Corporation

Inventor： Steven Towle ,  John Tang ,  John S. Cuendet ,  Henning Braunisch ,  Thomas S. Dory

IPC: H01L021/44

CPC classification number: H01L23/5389 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15173 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

Abstract translation: 低成本微电子电路封装包括在微电子管芯上方的单个堆积金属化层。 使用例如封装材料将至少一个管芯固定在封装芯内。 然后在模具/芯组件上构建单个金属化层。 金属化层包括许多具有允许微电子器件直接安装到外部电路板的间距的着陆焊盘。 在一个实施例中，金属化层包括在该层的外围区域内的多个信号着陆焊盘以及朝向该层的中心区域的至少一个电源着陆焊盘和一个接地焊盘。

公开(公告)号：US20040118604A1

公开(公告)日：2004-06-24

申请号：US10322902

申请日：2002-12-18

Applicant: Intel Corporation

Inventor： Thomas S. Dory ,  Michael Walk

IPC: H05K001/11

CPC classification number: H05K3/107 ,  H05K1/0373 ,  H05K3/0014 ,  H05K3/005 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1189 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: To decrease the complexity, time, and cost of fabricating an electronics package, and to potentially increase the quality and decrease the size thereof, the package includes at least one electronic component mounted on a substrate formed through imprinting. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Conductor features of different geometries may be formed by imprinting them simultaneously on one or both surfaces of an imprintable tape. Fabrication apparatus and methods, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract translation: 为了降低制造电子封装的复杂性，时间和成本，并且潜在地提高质量并减小其尺寸，封装包括安装在通过压印形成的衬底上的至少一个电子部件。 在一个实施例中，衬底可以包括导电迹线，通路和一个或多个层上的焊盘图案。 不同几何形状的导体特征可以通过将它们同时压印在可压印带的一个或两个表面上而形成。 还描述了制造装置和方法，以及将压印包装应用于电子组件。

公开(公告)号：US20030168342A1

公开(公告)日：2003-09-11

申请号：US10386981

申请日：2003-03-12

Applicant: Intel Corporation

Inventor： Kishore K. Chakravorty ,  Thomas S. Dory ,  C. Michael Garner

IPC: C25B009/00 ,  C25D017/00 ,  C25D005/02

CPC classification number: H05K1/162 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09809 ,  H05K2203/0315 ,  Y10T29/43

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract translation: 同轴电容器的各种实施例是自对准的，并且形成在通孔中，包括盲孔，埋入通孔和电镀通孔。 同轴电容器适于利用电镀通孔的电镀作为第一电极。 形成电介质层以覆盖第一电极，同时留下通孔的一部分未填充。 第二电极形成在未被电介质层填充的通孔左侧的部分中。 这种同轴电容器适用于去耦和功率衰减应用，以减少信号和功率噪声和/或减少电子设备中的功率过冲和下降。 对于这样的应用，通常期望通常以千位数字编号的多个同轴电容器将并联耦合，以便实现期望的电容水平。

公开(公告)号：US20040118594A1

公开(公告)日：2004-06-24

申请号：US10323165

申请日：2002-12-18

Applicant: Intel Corporation

Inventor： Thomas S. Dory ,  Michael Walk ,  Robert L. Sankman ,  Boyd L. Coomer

IPC: H05K003/20 ,  H05K001/11

CPC classification number: H05K3/107 ,  H05K3/0014 ,  H05K3/005 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: To decrease the complexity, time, and cost of fabricating an electronics package, and to potentially increase the quality and decrease the size thereof, the package includes at least one electronic component mounted on an imprinted substrate. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Such features may be formed by imprinting in one operation rather than sequentially. Conductor features, such as trenches, holes, and planes, may be formed of different sizes simultaneously. Methods of fabrication, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract translation: 为了降低制造电子封装的复杂性，时间和成本，并且潜在地提高质量并减小其尺寸，封装包括安装在压印基板上的至少一个电子部件。 在一个实施例中，衬底可以包括导电迹线，通路和一个或多个层上的焊盘图案。 这些特征可以通过在一个操作中打印而不是顺序地形成。 诸如沟槽，孔和平面的导体特征可以同时由不同尺寸形成。 还描述了制造方法以及将印刷包装应用于电子组件。