公开(公告)号：US20170181263A1

公开(公告)日：2017-06-22

申请号：US14974594

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Emad Al-Momani ,  Srikanth Mothukuri

IPC: H05K1/02 ,  H05K3/30 ,  H05K1/18 ,  G06F1/20 ,  H05K1/09

CPC classification number: H05K1/0203 ,  G06F1/20 ,  H01L23/4006 ,  H05K1/181 ,  H05K3/301 ,  H05K7/2039 ,  H05K7/2049 ,  H05K2201/066 ,  H05K2201/09909 ,  H05K2201/10325 ,  H05K2201/2018

Abstract: The present disclosure provides systems and methods for a package securing system including a top plate, an alignment frame, a gasket, and a back plate. The top plate comprises a thermal conductive member to transfer heat from a central processing unit (CPU) and secure the CPU to a ball grid array (BGA) socket and a printed circuit board (PCB). The alignment frame is configured to align a connection between the BGA socket and the PCB. The gasket is to seal the CPU, the BGA socket, and the alignment frame between the PCB and the top plate. The back plate is configured to couple with the top plate through the PCB.

公开(公告)号：US10334715B2

公开(公告)日：2019-06-25

申请号：US14974594

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Emad Al-Momani ,  Srikanth Mothukuri

IPC: H05K1/02 ,  H05K7/20 ,  H01L23/40 ,  G06F1/20 ,  H05K1/18

Abstract: The present disclosure provides systems and methods for a package securing system including a top plate, an alignment frame, a gasket, and a back plate. The top plate comprises a thermal conductive member to transfer heat from a central processing unit (CPU) and secure the CPU to a ball grid array (BGA) socket and a printed circuit board (PCB). The alignment frame is configured to align a connection between the BGA socket and the PCB. The gasket is to seal the CPU, the BGA socket, and the alignment frame between the PCB and the top plate. The back plate is configured to couple with the top plate through the PCB.

公开(公告)号：US09844144B1

公开(公告)日：2017-12-12

申请号：US15231018

申请日：2016-08-08

Applicant: Intel Corporation

Inventor： Emad Al-Momani ,  Jack Mumbo ,  Srikanth Mothukuri

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01R13/2421 ,  H05K3/325 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10393 ,  H05K2201/10409 ,  H05K2201/1056 ,  H05K2201/10598 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design are disclosed herein. In embodiments, an apparatus to mount an integrated circuit (IC) package, may include a printed circuit board (PCB), a plurality of pogo pins, and a mounting mechanism. The plurality of pogo pins may be mounted to electrical contacts of the PCB, the plurality of pogo pins may be coupled to the electrical contacts at first ends of the plurality of pogo pins and may be to couple to the IC package at second ends of the plurality of pogo pins. The mounting mechanism may position the IC package on the second ends of the plurality of pogo pins. Other embodiments may be described and/or claimed.