公开(公告)号：US20180231809A1

公开(公告)日：2018-08-16

申请号：US15751714

申请日：2015-08-11

Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION

Inventor： Kenichiro Yashiki ,  Yasuyuki Suzuki

IPC: G02F1/035 ,  G02F1/03 ,  G02F1/01 ,  H04B10/516

CPC classification number: G02F1/0356 ,  G02F1/011 ,  G02F1/0121 ,  G02F1/025 ,  G02F1/0327 ,  G02F2201/12 ,  H04B10/516

Abstract: The purpose of the present invention is to allow a silicon photonics modulator to be operated at high speed with high frequency by providing an electrode structure for the small multichannel high-density silicon photonics modulator. This electrode structure for a silicon photonics modulator includes, on the planar surface of a silicon substrate, a first layer for forming a plurality of bias electrical wirings, and a second layer formed by aligning each of a plurality of ground electrode portions and each electrical wiring in the first layer.

公开(公告)号：US10353225B2

公开(公告)日：2019-07-16

申请号：US15751714

申请日：2015-08-11

Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION

Inventor： Kenichiro Yashiki ,  Yasuyuki Suzuki

IPC: G02F1/01 ,  G02F1/03 ,  G02F1/025 ,  G02F1/035 ,  H04B10/516

Abstract: The purpose of the present invention is to allow a silicon photonics modulator to be operated at high speed with high frequency by providing an electrode structure for the small multichannel high-density silicon photonics modulator. This electrode structure for a silicon photonics modulator includes, on the planar surface of a silicon substrate, a first layer for forming a plurality of bias electrical wirings, and a second layer formed by aligning each of a plurality of ground electrode portions and each electrical wiring in the first layer.

公开(公告)号：US09772461B2

公开(公告)日：2017-09-26

申请号：US15023351

申请日：2014-10-01

Applicant: Photonics Electronics Technology Research Association

Inventor： Yasuyuki Suzuki ,  Kenichiro Yashiki ,  Kazuhiko Kurata

IPC: G02B6/12 ,  G02B6/136 ,  G02B6/42 ,  G02B6/122 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  G02F1/025

CPC classification number: G02B6/428 ,  G02B6/12 ,  G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02F1/025 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/16225

Abstract: A semiconductor integrated circuit that reduces a loss in an electrical signal and a method for manufacturing the semiconductor integrated circuit are provided. The semiconductor integrated circuit comprises a first region on which an optical circuit is to be formed and a second region on which an electrical signal wiring is to be formed. The first region comprises an Si substrate (502), a BOX layer (504) formed on the Si substrate (502), a first SOI layer (506) formed as an optical circuit on the BOX layer (504), and a first SiO2 layer (508) formed on the first SOI layer (506). The second region comprises the Si substrate (502), the BOX layer (504), a second SiO2 layer (508) formed on the BOX layer (504), and an electrical signal wiring (510) formed on the second SiO2 layer (508).

公开(公告)号：US20160245691A1

公开(公告)日：2016-08-25

申请号：US15023354

申请日：2014-10-01

Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION

Inventor： Yasuyuki Suzuki ,  Daisuke Okamoto

IPC: G01J1/44 ,  H01L27/144 ,  H01L31/028 ,  H01L21/02 ,  H01L31/18 ,  H01L21/768 ,  H04B10/60 ,  H01L31/02

CPC classification number: G01J1/44 ,  G01J2001/446 ,  H01L21/02164 ,  H01L21/768 ,  H01L27/1443 ,  H01L31/02005 ,  H01L31/028 ,  H01L31/1808 ,  H03F1/083 ,  H03F3/08 ,  H04B10/60 ,  H04B10/693

Abstract: An optical receiving circuit which suppresses a characteristic deterioration due to a wiring between a PD and a TIA and a method for manufacturing the optical receiving circuit are provided. A optical receiving circuit (300) comprises a photodiode (302), and a transimpedance amplifier (308) that supplies an electrical power source to the photodiode (302). The characteristic impedance of a wiring between the anode of the photodiode (302) and the transimpedance amplifier (308) is higher than the characteristic impedance of a wiring between the cathode of the photodiode (302) and the transimpedance amplifier (308).

Abstract translation: 提供抑制由于PD与TIA之间的布线导致的特性恶化的光接收电路以及光接收电路的制造方法。 光接收电路（300）包括光电二极管（302）和向光电二极管（302）提供电源的跨阻放大器（308）。 光电二极管（302）的阳极和跨阻放大器（308）之间的布线的特性阻抗高于光电二极管（302）的阴极与跨阻放大器（308）之间的布线的特性阻抗。

公开(公告)号：US10048124B2

公开(公告)日：2018-08-14

申请号：US15023354

申请日：2014-10-01

Applicant: Photonics Electronics Technology Research Association

Inventor： Yasuyuki Suzuki ,  Daisuke Okamoto

IPC: H03F3/08 ,  G01J1/44 ,  H04B10/60 ,  H01L21/02 ,  H01L21/768 ,  H01L27/144 ,  H01L31/02 ,  H01L31/028 ,  H01L31/18 ,  H03F1/08

Abstract: An optical receiving circuit which suppresses a characteristic deterioration due to a wiring between a PD and a TIA and a method for manufacturing the optical receiving circuit are provided. A optical receiving circuit (300) comprises a photodiode (302), and a transimpedance amplifier (308) that supplies an electrical power source to the photodiode (302). The characteristic impedance of a wiring between the anode of the photodiode (302) and the transimpedance amplifier (308) is higher than the characteristic impedance of a wiring between the cathode of the photodiode (302) and the transimpedance amplifier (308).

公开(公告)号：US20160266333A1

公开(公告)日：2016-09-15

申请号：US15023351

申请日：2014-10-01

Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION

Inventor： Yasuyuki Suzuki ,  Kenichiro Yashiki ,  Kazuhiko Kurata

IPC: G02B6/42 ,  G02B6/136 ,  G02F1/025 ,  G02B6/122

CPC classification number: G02B6/428 ,  G02B6/12 ,  G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02F1/025 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/16225

Abstract: A semiconductor integrated circuit that reduces a loss in an electrical signal and a method for manufacturing the semiconductor integrated circuit are provided. The semiconductor integrated circuit comprises a first region on which an optical circuit is to be formed and a second region on which an electrical signal wiring is to be formed. The first region comprises an Si substrate (502), a BOX layer (504) formed on the Si substrate (502), a first SOI layer (506) formed as an optical circuit on the BOX layer (504), and a first SiO2 layer (508) formed on the first SOI layer (506). The second region comprises the Si substrate (502), the BOX layer (504), a second SiO2 layer (508) formed on the BOX layer (504), and an electrical signal wiring (510) formed on the second SiO2 layer (508).

Abstract translation: 提供减少电信号损耗的半导体集成电路和半导体集成电路的制造方法。 半导体集成电路包括要在其上形成光电路的第一区域和要在其上形成电信号布线的第二区域。 第一区域包括Si衬底（502），形成在Si衬底（502）上的BOX层（504），在BOX层（504）上形成为光电路的第一SOI层（506）和第一SiO 2 层（508）形成在第一SOI层（506）上。 第二区域包括Si衬底（502），BOX层（504），形成在BOX层（504）上的第二SiO 2层（508）和形成在第二SiO 2层（508）上的电信号布线 ）。