公开(公告)号：US08510629B2

公开(公告)日：2013-08-13

申请号：US12908512

申请日：2010-10-20

Applicant: Wataru Tsukada ,  Shiro Harashima ,  Yoji Nishio

Inventor： Wataru Tsukada ,  Shiro Harashima ,  Yoji Nishio

IPC: G11C29/00

CPC classification number: G06F11/1044 ,  H03M13/13

Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.

Abstract translation: 将其中存储用户数据的常规芯片封装和存储其中的纠错码的纠错芯片封装安装在模块基板上。 模块基板在X方向上具有不同坐标的第一和第二安装区域，并且第二安装区域具有不同Y坐标的第三和第四安装区域。 常规包装件相对地布置在模块基板的表面和背面上的第一安装区域中。 纠错芯片封装相对地布置在模块基板的表面和背面上的第三安装区域中。 缓冲用户数据和纠错码的存储器缓冲器布置在第四安装区域中。

公开(公告)号：US08462535B2

公开(公告)日：2013-06-11

申请号：US13549949

申请日：2012-07-16

Applicant: Shiro Harashima ,  Wataru Tsukada

Inventor： Shiro Harashima ,  Wataru Tsukada

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。

公开(公告)号：US08243488B2

公开(公告)日：2012-08-14

申请号：US13270587

申请日：2011-10-11

Applicant: Shiro Harashima ,  Wataru Tsukada

Inventor： Shiro Harashima ,  Wataru Tsukada

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。

公开(公告)号：US20110093764A1

公开(公告)日：2011-04-21

申请号：US12908512

申请日：2010-10-20

Applicant: Wataru TSUKADA ,  Shiro Harashima ,  Yoji Nishio

Inventor： Wataru TSUKADA ,  Shiro Harashima ,  Yoji Nishio

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G06F11/1044 ,  H03M13/13

Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.

Abstract translation: 将其中存储用户数据的常规芯片封装和存储其中的纠错码的纠错芯片封装安装在模块基板上。 模块基板在X方向上具有不同坐标的第一和第二安装区域，并且第二安装区域具有不同Y坐标的第三和第四安装区域。 常规包装件相对地布置在模块基板的表面和背面上的第一安装区域中。 纠错芯片封装相对地布置在模块基板的表面和背面上的第三安装区域中。 缓冲用户数据和纠错码的存储器缓冲器布置在第四安装区域中。

公开(公告)号：US08773883B2

公开(公告)日：2014-07-08

申请号：US13610282

申请日：2012-09-11

Applicant: Shiro Harashima

Inventor： Shiro Harashima

IPC: G11C5/06 ,  G06F13/00 ,  G06F12/06

CPC classification number: G11C5/06 ,  G06F12/06 ,  G06F12/0623 ,  G11C5/04 ,  G11C5/063

Abstract: A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.

Abstract translation: 一种系统包括：控制器，通过第一数据总线连接到控制器的第一存储器模块和通过第二数据总线连接到控制器的第二存储器模块，其中第一存储器模块包括：第一和第二存储器芯片; 连接到第一数据总线的第一数据终端和将第一数据终端与第一存储器芯片和第二存储器芯片电连接的第一开关单元，并且第二模块包括：第三和第四存储器芯片; 连接到第二数据总线的第二数据终端，以及第二开关单元，其切换第二数据终端与第三存储器芯片或第四存储器芯片的电连接。

公开(公告)号：US20120026772A1

公开(公告)日：2012-02-02

申请号：US13270587

申请日：2011-10-11

Applicant: Shiro Harashima ,  Wataru Tsukada

Inventor： Shiro Harashima ,  Wataru Tsukada

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。

公开(公告)号：US20120281348A1

公开(公告)日：2012-11-08

申请号：US13549949

申请日：2012-07-16

Applicant: Shiro Harashima ,  Wataru Tsukada

Inventor： Shiro Harashima ,  Wataru Tsukada

IPC: H05K7/06

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

公开(公告)号：US20110051351A1

公开(公告)日：2011-03-03

申请号：US12805264

申请日：2010-07-21

Applicant: Shiro Harashima

Inventor： Shiro Harashima

IPC: G06F1/16 ,  H01R12/30 ,  H05K7/02

CPC classification number: H05K1/117 ,  H01R12/721 ,  H05K1/0263 ,  H05K1/0298 ,  H05K3/0052 ,  H05K3/403 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09345

Abstract: A circuit board according to the present invention includes a main surface, a back surface parallel to the main surface, a side surface positioned between edges of the main surface and the back surface, and first and second board terminals covering a portion of the main surface and a portion of the side surface, respectively. According to the present invention, because the board terminals are provided not only on the main surface but also on the side surface of the circuit board, the total number of board terminals can be increased while maintaining sufficient pitch and width of the board terminals.

Abstract translation: 根据本发明的电路板包括主表面，平行于主表面的后表面，位于主表面和后表面的边缘之间的侧表面，以及覆盖主表面的一部分的第一和第二板端子 和侧面的一部分。 根据本发明，由于电路板端子不仅设置在电路板的主表面上，而且还设置在电路板的侧表面上，所以可以在保持板端子的足够的间距和宽度的同时增加电路板端子的总数。

公开(公告)号：US08054664B2

公开(公告)日：2011-11-08

申请号：US12638382

申请日：2009-12-15

Applicant: Shiro Harashima ,  Wataru Tsukada

Inventor： Shiro Harashima ,  Wataru Tsukada

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。

公开(公告)号：US20100157645A1

公开(公告)日：2010-06-24

申请号：US12638382

申请日：2009-12-15

Applicant: Shiro Harashima ,  Wataru Tsukada

Inventor： Shiro Harashima ,  Wataru Tsukada

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/10

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。