公开(公告)号：US20250159872A1

公开(公告)日：2025-05-15

申请号：US18746811

申请日：2024-06-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yaqin LIU ,  Wei LIU ,  ZhiLiang XIA ,  ZongLiang HUO ,  Yuancheng YANG ,  DongXue ZHAO

IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4091

Abstract: Implementations of the present application provide a semiconductor device, a fabrication method thereof and a memory system. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The second semiconductor structure is disposed on a side of the first semiconductor structure in the first direction and in direct contact with the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells, the first semiconductor structure includes a first peripheral circuit connected with the plurality of memory cells, and in the plane perpendicular to the first direction, at least a portion of the first peripheral circuit is located directly below the plurality of memory cells, wherein the first peripheral circuit includes at least one of a driving structure and a sensing structure.

公开(公告)号：US20240282376A1

公开(公告)日：2024-08-22

申请号：US18631706

申请日：2024-04-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： DongXue ZHAO ,  Tao YANG ,  Yuancheng YANG ,  Lei LIU ,  Di WANG ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.

公开(公告)号：US20240164107A1

公开(公告)日：2024-05-16

申请号：US18147555

申请日：2022-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DongXue ZHAO ,  Tao YANG ,  Wenxi ZHOU ,  Yuancheng YANG ,  ZhiLiang XIA ,  ZongLiang HUO

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: The present disclosure provides a memory device that includes a film stack having functional tiers stacked in a first direction. Each functional tier includes a first dielectric layer and a conductive layer. The memory device also includes channel structures disposed in an array core region, wherein each channel structure extends through the film stack in the first direction. Each channel structure includes a control gate in a center, a memory film that is disposed on a sidewall of the control gate and includes a ferroelectric film. Each channel structure also includes a channel layer disposed on a sidewall of the memory film.

公开(公告)号：US20230142290A1

公开(公告)日：2023-05-11

申请号：US17646549

申请日：2021-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DongXue ZHAO ,  Tao Yang ,  Yuancheng Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  ZongLiang Huo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.