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公开(公告)号：WO2022250283A1
公开(公告)日：2022-12-01
申请号：PCT/KR2022/005029
申请日：2022-04-07
Applicant: 국민대학교산학협력단
Abstract: 본 발명은 광학적 특성 저장 디바이스 및 이를 이용하는 시스템에 관한 것이다. 본 발명의 일 실시예에 따른 디바이스는, 입사광이 가지는 색온도 및 조도의 광학적 특성에 따라 소스 전극 및 드레인 전극 사이의 컨덕턴스(conductance)가 가변되는 광 트랜지스터; 및 제1 전극이 광 트랜지스터의 소스 및 드레인 전극 중 어느 한 전극에 전기적으로 연결되며, 광 트랜지스터의 가변된 컨덕턴스에 따라 가변되는 컨덕턴스를 저장하는 2단자의 가변 저항 메모리 소자;를 포함한다.
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3.发明授权
公开(公告)号：KR101621687B1
公开(公告)日：2016-05-18
申请号：KR1020140008467
申请日：2014-01-23
Applicant: 국민대학교산학협력단
IPC: G01N27/416 , G01N27/327 , G01N27/403
Abstract: 본발명은바이오센서및 감지방법에관한것으로, 보다상세하게는하향식(top-down approach) 제조공정을이용하여반도체소자로이루어진바이오센싱부와타겟물질의상태변수에상응하는전류신호를증폭하는증폭부가집적된바이오센서및 바이오물질감지방법에관한것이다. 본발명은상기와같은종래기술의문제점을해결하고자도출된것으로서, 하향식(top-down approach) 제조공정을이용하여바이오센서부분과증폭회로를단일계열의공정으로형성하고, 이로인하여바이오센서및 증폭회로의공정편차를줄일뿐 아니라바이오센서와증폭회로를단일칩 상에용이하게집적할수 있어소형화를달성할수 있는바이오센서및 바이오물질감지방법을제안하는것을목적으로한다.
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公开(公告)号：KR101621686B1
公开(公告)日：2016-05-18
申请号：KR1020140001468
申请日：2014-01-06
Applicant: 국민대학교산학협력단
IPC: G01N27/416 , G01N27/403
Abstract: 본발명은디지털화기법을이용한바이오물질감지시스템및 감지장치에관한것으로, 보다상세하게는상호보완적인(Complementary) 반도체소자로이루어진바이오센서로부터수신신호를수신하여디지털화신호처리부(Digitizer)에서타겟물질의상태변수를결정하는바이오물질감지시스템및 감지장치에관한것이다. 본발명에서는반도체특성을가지는나노소자의바이어스조건에대한바이오물질과수용체(receptor)의반응에따른감지신호의노이즈가제거된수신신호를수신하여상태변수에따라디지털화된비트(digitizer bit)의테이블을측정하고, 측정된디지털레벨각각을저장하여바이오물질의검출속도를높이고, 민감도를높이는것을목적으로한다.
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5.发明授权게이트-드레인 및 게이트-소스의 커패시턴스-전압 특성을 이용한 저온 다결정 실리콘 박막 트랜지스터의 결정립 경계위치를 추적하는 장치 및 방법 有权通过在LTPS TFTS中使用门到漏和门到源C-V配置来分析谷物边界的分析装置和方法
公开(公告)号：KR101531667B1
公开(公告)日：2015-06-26
申请号：KR1020140066080
申请日：2014-05-30
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786
CPC classification number: H01L22/14 , H01L22/12 , H01L29/78672
Abstract: 본발명은다결정박막트랜지스터에서결정립계가존재하지않는경우의게이트-드레인, 게이트-소스의커패시턴스-전압특성과결정립계가존재하는경우의게이트-드레인, 게이트-소스의커패시턴스-전압특성의차를이용하여결정립계의위치에의존하는커패시턴스의변화()를추출하고최종적으로는결정립계의위치를계산을통해추출하는장치및 방법을제공하기위한것으로서, 결정립계가소자의채널내에존재하지않는경우의커패시턴스-전압특성및 결정립계가소자의채널내에존재하는경우의커패시턴스-전압특성을각각검출하는커패시턴스-전압특성검출모듈과, 상기커패시턴스-전압특성검출모듈에서검출된각각의커패시턴스-전압특성을서로비교하고그 결과의차를이용하여커패시턴스의변화()를추출하는커패시턴스변화추출부와, 상기커패시턴스변화추출부에서추출된커패시턴스의변화를이용하여소자의채널내 결정립계의위치를산출하는결정립경계위치산출부를포함하여구성되는데있다.
Abstract translation: 本发明是提供一种装置和方法，其通过使用栅极 - 漏极和栅极 - 源极的电容 - 电压特性的差异来提取取决于晶粒位置的电容的变化，当晶粒不是 存在于多晶硅薄膜晶体管中，并且当存在晶粒时使用栅极 - 漏极和栅极 - 源极的电容 - 电压特性的差异，并且最终通过计算提取晶粒的位置。 该装置包括：电容电压特性检测模块，用于当晶体存在于器件的沟道内时分别检测电容 - 电压特性;以及当晶粒不存在于器件的沟道中时的电容 - 电压特性; 电容变化提取单元，通过使用电容电压特性检测模块分别检测出的电容电压特性之差通过比较电容电压特性来提取电容的变化（C_gb.X_GB）; 以及晶界边界位置计算单元，通过使用由电容变化提取单元提取的电容的变化来计算器件的沟道内的晶粒的位置。
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Patent Agency Ranking6.发明授权채널 전도 계수를 이용한 비정질 산화물 반도체 박막 트랜지스터의 진성 밴드갭 내 상태밀도 추출 방법 및 그 장치 有权使用通道导通因子及其装置提取非晶氧化物半导体薄膜晶体管的内在子像素密度的方法
公开(公告)号：KR101427713B1
公开(公告)日：2014-08-07
申请号：KR1020130112514
申请日：2013-09-23
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786
CPC classification number: H01L22/12 , H01L22/30 , H01L29/78693
Abstract: A method for extracting intrinsic subgap density of states of an amorphous oxide semiconductor thin film transistor using a channel conduction factor, and a device thereof are disclosed. The method for extracting the intrinsic subgap density of states of the amorphous oxide semiconductor thin film transistor according to an embodiment of the present invention comprises a step of measuring capacitance according to a gate voltage of the thin film transistor; a step of extracting a conduction factor of a channel according to the gate voltage using the measured capacitance; and a step of extracting intrinsic subgap density of states based on the conduction factor of the extracted channel. The step of extracting the intrinsic subgap density of states replaces a physical length between source and drain electrodes with a length of a variable of the conduction factor of the channel and extracts the intrinsic subgap density of states considering the conduction factor of the channel.
Abstract translation: 公开了一种使用沟道导通因数提取非晶氧化物半导体薄膜晶体管的本征子陷阱密度的方法及其装置。 根据本发明实施例的用于提取非晶氧化物半导体薄膜晶体管的本征子陷阱密度的方法包括根据薄膜晶体管的栅极电压测量电容的步骤; 使用测量的电容根据栅极电压提取沟道的导通因数的步骤; 以及基于提取的通道的导通因数来提取状态的内在子陷阱密度的步骤。 提取状态的固有子间隙密度的步骤取代了源极和漏极之间的物理长度，其长度为通道的导通因子的变量的长度，并且考虑通道的导通因数提取状态的内在子陷阱密度。
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公开(公告)号：KR1020140043526A
公开(公告)日：2014-04-10
申请号：KR1020120105381
申请日：2012-09-21
Applicant: 삼성디스플레이 주식회사 , 국민대학교산학협력단
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/7869 , H01L29/41733 , H01L29/66969 , H01L29/78693 , H01L33/387 , H01L29/78696
Abstract: A thin film transistor display array is provided. A thin film transistor display array according to one embodiment of the present invention includes a substrate, a gate electrode which is located on the substrate, a gate insulating layer which is located on the gate electrode, a semiconductor layer which is located on the gate insulating layer, a source and a drain electrode which are located on the semiconductor layer and faces each other, a floating metal layer which is located between the source and the drain electrode, and a protection layer which covers the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floated.
Abstract translation: 提供薄膜晶体管显示阵列。 根据本发明的一个实施例的薄膜晶体管显示阵列包括基板，位于基板上的栅电极，位于栅电极上的栅极绝缘层，位于栅绝缘层上的半导体层 层，源极和漏极，其位于半导体层上并且彼此面对，位于源极和漏极之间的浮动金属层以及覆盖源电极，漏极和保护层的保护层 浮动金属层。 浮动金属层电浮动。
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公开(公告)号：KR101344752B1
公开(公告)日：2013-12-24
申请号：KR1020130027986
申请日：2013-03-15
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786
CPC classification number: H01L22/12 , H01L22/30 , H01L29/78693
Abstract: A method for extracting the density of state within an intrinsic band gap of an amorphous oxide semiconductor thin film transistor and a device thereof are disclosed. The method for extracting the density of state within the intrinsic band gap of the amorphous oxide semiconductor thin film transistor comprises; a step of measuring darkroom capacitance according to gate voltage of a thin film transistor; a step of measuring light reaction capacitance of the thin film transistor by irradiating the thin film transistor with a light source of a predetermined wavelength; a step of calculating intrinsic capacitance of the thin film transistor based on the darkroom capacitance and the light reaction capacitance; and a step of extracting the density of state within the intrinsic band gap of the thin film transistor based on the calculated intrinsic capacitance. The step of calculating the intrinsic capacitance extracts the density of state within an independent intrinsic band gap to parasitic capacitance by calculating the intrinsic capacitance after de-embedding the parasitic capacitance of the thin film transistor at the darkroom capacitance and the light reaction capacitance. [Reference numerals] (AA) Start;(BB) End;(S310) Darkroom capacitance according to gate voltage is measured in a darkroom;(S320) Light reaction capacitance according to gate voltage is measured by irradiating a light source;(S330) Intrinsic capacitance is calcualted based on measured darkroom capacitance and light reaction capacitance;(S340) Density of state within a intrinsic band gap is extracted based on calculated intrinsic capacitance
Abstract translation: 公开了一种用于提取非晶氧化物半导体薄膜晶体管的固有带隙内的状态密度的方法及其装置。 提取非晶氧化物半导体薄膜晶体管的本征带隙内的状态密度的方法包括： 根据薄膜晶体管的栅极电压测量暗室电容的步骤; 通过用预定波长的光源照射薄膜晶体管来测量薄膜晶体管的光反应电容的步骤; 基于暗室电容和光反应电容计算薄膜晶体管的本征电容的步骤; 以及基于所计算的本征电容提取薄膜晶体管的本征带隙内的状态密度的步骤。 计算本征电容的步骤通过计算在薄膜晶体管的寄生电容在暗室电容和光反应电容中去嵌入之后计算固有电容，将独立的固有带隙内的状态密度提取到寄生电容。 （参考号）（AA）开始;（BB）结束;（S310）根据栅极电压的暗室电容在暗室中测量;（S320）通过照射光源测量根据栅极电压的光反应电容;（S330） 基于测量的暗室电容和光反应电容计算本征电容;（S340）根据计算出的本征电容提取本征带隙内的状态密度
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公开(公告)号：KR100956798B1
公开(公告)日：2010-05-11
申请号：KR1020090064187
申请日：2009-07-14
Applicant: 국민대학교산학협력단
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/28282 , G11C16/04 , H01L21/265 , H01L21/31051
Abstract: PURPOSE: A manufacturing method of a non-volatile memory cell and a NOR type memory architecture thereof are provided to improve whole memory integration degree by using a non-volatile memory. CONSTITUTION: A character-I like active fin forming a source/drain region on both sides is patterned(S110). An oxide film is deposited(S120). A first oxide film is formed in the active fin region(S130). A character-T like gate is patterned by using a hard mask pattern as the mask on a deposited polysilicon. A second oxide film is formed in the gate region(S150). A charge trapped layer is formed between the first oxide film and the second oxide film(S160).
Abstract translation: 目的：提供一种非易失性存储单元及其NOR型存储器结构的制造方法，以通过使用非易失性存储器来提高整体存储器集成度。 构成：在两面形成源极/漏极区域的字符I像活性鳍形成图案（S110）。 沉积氧化膜（S120）。 在活性鳍片区域形成第一氧化膜（S130）。 通过使用硬掩模图案作为沉积的多晶硅上的掩模来将字符T样栅极图案化。 在栅极区域形成第二氧化膜（S150）。 在第一氧化膜和第二氧化物膜之间形成电荷捕获层（S160）。
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公开(公告)号：KR1020170041324A
公开(公告)日：2017-04-17
申请号：KR1020150140427
申请日：2015-10-06
Applicant: 국민대학교산학협력단
IPC: H01L29/786 , H01L29/06 , H01L21/02 , H01L51/00
Abstract: 본발명은고밀도탄소나노튜브네트워크박막트랜지스터및 나노메시공정에관한것이다. 본발명의일 양상인탄소나노튜브박막트랜지스터는, 기판; 상기기판상부에형성되며, 탄소나노튜브네트워크박막으로이루어진채널층; 상기채널층상부에형성되는소오스/드레인전극; 상기소오스/드레인전극상부에형성되는절연층; 및상기절연층상부에형성되는게이트전극을포함하고, 상기탄소나노튜브네트워크박막의적어도일부가구멍이뚫려있는메쉬(mesh) 구조일수 있다.
Abstract translation: 本发明涉及高密度碳纳米管网络薄膜晶体管和纳米网格工艺。 本发明的一个方面是一种碳纳米管薄膜晶体管，包括：衬底; 形成在所述基板上的沟道层，所述沟道层包括碳纳米管网络薄膜; 形成在沟道层上的源极/漏极电极; 形成在源极/漏极上的绝缘层; 以及形成在绝缘层上的栅电极，碳纳米管网络薄膜可以具有网状结构，其中碳纳米管网状薄膜的至少一部分被穿孔。
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