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公开(公告)号：US20240008171A1
公开(公告)日：2024-01-04
申请号：US18143133
申请日：2023-05-04
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Wei-Teng Lin , Hui-Yu Huang , Ching-Chi Chan , Shih-Chieh Chang
IPC: H05K1/02 , H01L23/00 , H01L23/498
CPC classification number: H05K1/0272 , H01L24/32 , H01L23/49838 , H01L23/4985 , H01L2224/32225 , H01L2224/26175 , H01L2924/15151
Abstract: A semiconductor package includes a chip, a circuit board and a filling material. The circuit board includes a substrate, a patterned metal layer and a protective layer. A circuit area, a chip-mounting area and a flow-guiding area are defined on a surface of the substrate. The chip is mounted on the chip-mounting area. A flow-guiding member of the patterned metal layer is arranged on the flow-guiding area and includes a hollow portion and flow-guiding grooves which are communicated with the hollow portion and arranged radially. The flow-guiding grooves are provided to allow the protective layer to flow toward the hollow portion, and the hollow portion and the flow-guiding grooves are provided to allow the filling material to flow toward the protective layer such that the filling material can cover the protective layer to improve structural strength of the semiconductor package.
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公开(公告)号：US20220110209A1
公开(公告)日：2022-04-07
申请号：US17470038
申请日：2021-09-09
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Shih-Chieh Chang , Hui-Yu Huang , Chih-Ming Peng , Chun-Te Lee
Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.
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公开(公告)号：US08823169B2
公开(公告)日：2014-09-02
申请号：US13644749
申请日：2012-10-04
Applicant: Chipbond Technology Corporation
Inventor： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
CPC classification number: H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
Abstract translation: 半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部， 突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖 突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。
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公开(公告)号：US20140217578A1
公开(公告)日：2014-08-07
申请号：US13833347
申请日：2013-03-15
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Lung-Hua Ho , Fei-Jain Wu , Chih-Ming Kuo , Shih-Chieh Chang , Chia-Jung Tu
IPC: H01L23/00
CPC classification number: H01L24/81 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/13006 , H01L2224/13016 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13562 , H01L2224/1601 , H01L2224/16503 , H01L2224/81048 , H01L2224/81193 , H01L2224/81203 , H01L2224/81898 , H01L2924/1461 , H01L2924/00 , H01L2924/00014 , H01L2924/01047 , H01L2924/00012
Abstract: A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state.
Abstract translation: 半导体封装工艺包括以下步骤：提供具有第一金属凸块的第一衬底，第一金属凸块包括具有第一软化点的接合部分; 提供具有第二金属凸块的第二基板，其具有顶表面，侧表面和第二软化点，其中所述第一软化点小于所述第二软化点; 执行加热程序以使第一金属凸块的接合部分变为软化状态; 并且将所述第一基板层压在所述第二基板上，以使所述第二金属凸块以软化状态嵌入所述接合部，以使所述至少一个第二金属凸块的顶表面和所述侧表面通过压缩所述接合部分 软化状态。
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公开(公告)号：US20140021601A1
公开(公告)日：2014-01-23
申请号：US13644749
申请日：2012-10-04
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
CPC classification number: H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
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Patent Agency Ranking
公开(公告)号：US20250038130A1
公开(公告)日：2025-01-30
申请号：US18771070
申请日：2024-07-12
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Sheng-Han Yang , Shih-Chieh Chang
Abstract: A wafer includes chips, a scribe lane, a metal layer and an inhibitor made of a nonconductive material. The metal layer is provided on the scribe lane and the chip located next to the scribe lane. The inhibitor covers the scribe lane and the chip next to the scribe line and includes a first removed part and an inhibition part which are located above a second removed part and a residual part of the metal layer, respectively. The scribe lane, the first and second removed parts are removed, and the inhibition part and the residual part are retained on each of the chips after a wafer cutting process. The inhibitor is provided to prevent the residual part of the metal layer from being lifted up or generating a metal burr during the wafer cutting process.
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公开(公告)号：US11792923B2
公开(公告)日：2023-10-17
申请号：US17470038
申请日：2021-09-09
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Shih-Chieh Chang , Hui-Yu Huang , Chih-Ming Peng , Chun-Te Lee
CPC classification number: H05K1/0277 , H05K1/14 , H05K1/189 , H05K2201/09036
Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.
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公开(公告)号：US09159660B2
公开(公告)日：2015-10-13
申请号：US14042979
申请日：2013-10-01
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
IPC: H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00 , H01L25/065 , H01L21/48
CPC classification number: H01L23/49811 , H01L21/4846 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1147 , H01L2224/11472 , H01L2224/11831 , H01L2224/11903 , H01L2224/11906 , H01L2224/13011 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/8114 , H01L2224/81193 , H01L2224/81345 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/014
Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。
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公开(公告)号：US20140141606A1
公开(公告)日：2014-05-22
申请号：US14164628
申请日：2014-01-27
Applicant: Chipbond Technology Corporation
Inventor： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
IPC: H01L21/768
CPC classification number: H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
Abstract translation: 半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部， 突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖 突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。
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公开(公告)号：US20140027905A1
公开(公告)日：2014-01-30
申请号：US14042979
申请日：2013-10-01
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
IPC: H01L23/498
CPC classification number: H01L23/49811 , H01L21/4846 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1147 , H01L2224/11472 , H01L2224/11831 , H01L2224/11903 , H01L2224/11906 , H01L2224/13011 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/8114 , H01L2224/81193 , H01L2224/81345 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/014
Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。
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