公开(公告)号：WO2007082917A2

公开(公告)日：2007-07-26

申请号：PCT/EP2007050503

申请日：2007-01-18

Applicant: IBM ,  IBM UK ,  BORKENHAGEN JOHN MICHAEL ,  VANDERPOOL BRIAN

Inventor： BORKENHAGEN JOHN MICHAEL ,  VANDERPOOL BRIAN

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/128 ,  G06F12/0897

Abstract: A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.

Abstract translation: 计算机系统具有巡视侦听序列器，该序列通过保持在较高级别缓存中的缓存行的地址进行排序，从而使窥探将这些地址读取到较低级别的缓存。 如果保持在较高级高速缓存中的特定高速缓存行没有保持在较低级高速缓存中，则当新高速缓存行必须被加载到较高级高速缓存中时，特定高速缓存行被标识为较高级高速缓存中的驱逐候选者。

公开(公告)号：WO2007042428A2

公开(公告)日：2007-04-19

申请号：PCT/EP2006066999

申请日：2006-10-03

Applicant: IBM ,  IBM UK ,  BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  HOVIS WILLIAM PAUL ,  KOLZ DANIEL PAUL

Inventor： BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  HOVIS WILLIAM PAUL ,  KOLZ DANIEL PAUL

CPC classification number: G06F13/28

Abstract: An apparatus includes a virtual memory manager that moves data from a first block (A) to a second block (B) in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block (C) of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.

Abstract translation: 一种装置包括将数据从第一块（A）移动到存储器中的第二块（B）的虚拟存储器管理器。 当虚拟存储器管理器准备好将数据从第一块传送到第二块时，定义了第三个临时块（C）。 将DMA控制器中的转换表更改为将目标为第一个块的DMA传输指向临时块。 然后，虚拟存储器管理器将数据从第一块传送到第二块。 当传输完成时，检查DMA是否将数据传输到临时块，而第一个块的数据正在写入第二个块。 如果是这样，则将写入临时块的数据写入第二块。 优选地使用硬件寄存器来有效地检测对临时块的改变。

公开(公告)号：DE602008002436D1

公开(公告)日：2010-10-14

申请号：DE602008002436

申请日：2008-06-25

Applicant: IBM

Inventor： BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  GERMANN PHILIP RAYMOND

IPC: G06F13/16

公开(公告)号：PL193285B1

公开(公告)日：2007-01-31

申请号：PL34009598

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  WOTTRENG ANDREW HENRY

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/46 ,  G06F9/48

公开(公告)号：DE602007006277D1

公开(公告)日：2010-06-17

申请号：DE602007006277

申请日：2007-01-18

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  VANDERPOOL BRIAN

IPC: G06F12/12 ,  G06F12/08

公开(公告)号：DE602004007681T2

公开(公告)日：2008-04-30

申请号：DE602004007681

申请日：2004-09-10

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  ZUMBRUNNEN LAURA MARIE

IPC: G06F11/20 ,  G06F11/00 ,  H04L12/26 ,  H04L12/40

Abstract: Methods and apparatus are provided that allow an electronic system having a signaling bus with a fault on a signaling conductor to operate at a degraded performance. A block of data is transferred from a first electronic unit to a second electronic unit over the signaling bus. A transmission sequence sends the block of data using all of the nonfaulty signaling conductors using a minimum number of beats required to complete the transmission.

公开(公告)号：CA2299348C

公开(公告)日：2004-10-19

申请号：CA2299348

申请日：1998-10-14

Applicant: IBM

Inventor： WOTTRENG ANDREW HENRY ,  BORKENHAGEN JOHN MICHAEL ,  FLYNN WILLIAM THOMAS ,  EICKEMEYER RICHARD JAMES

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system (10) includes a multithreaded processor (100) and thread switch logic (400). The multithreaded processor is capable of switching between two or more threads of instractions which can be independently executed. Each thread has a corresponding state in a thread state register (440) depending on its execution status. The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread will occur. The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register (420) to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager (460) capable of changing the priority of the different threads and thus superseding thread switch events.

公开(公告)号：DE69012954T2

公开(公告)日：1995-04-06

申请号：DE69012954

申请日：1990-10-09

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  DOUSKEY STEVEN MICHAEL ,  MEYER JEROME MARTIN

IPC: G01R31/28 ,  G01R31/00 ,  G06F11/16 ,  G06F11/22 ,  G06F11/267 ,  G01R31/3177

Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing a oscillator input signal (12) to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) (20,30) are provided in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one (20) of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one (30) of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.

公开(公告)号：AT450831T

公开(公告)日：2009-12-15

申请号：AT06793956

申请日：2006-10-03

Applicant: IBM

Inventor： BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  HOVIS WILLIAM PAUL ,  KOLZ DANIEL PAUL

IPC: G06F13/28

公开(公告)号：HU0100013A2

公开(公告)日：2001-05-28

申请号：HU0100013

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  LEVENSTEIN SHELDON BERNARD ,  WOTTRENG ANDREW HENRY

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.