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    2.
    发明专利
    未知

    公开(公告)号：DE2527969A1

    公开(公告)日：1976-01-08

    申请号：DE2527969

    申请日：1975-06-24

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  RIDEOUT VINCENT LEO ,  WALKER EDWARD JOHN

    IPC: H01L27/088 ,  H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L21/18

    Abstract: Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistors (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide therein. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.

    METHOD OF PRODUCING FIELD-EFFECT TRANSISTORS OF THE MOS TYPE WITH SELF-ALIGNED GATE AND CONTACT VIAS
    4.
    发明专利
    METHOD OF PRODUCING FIELD-EFFECT TRANSISTORS OF THE MOS TYPE WITH SELF-ALIGNED GATE AND CONTACT VIAS 未知

    公开(公告)号：DE2967441D1

    公开(公告)日：1985-05-30

    申请号：DE2967441

    申请日：1979-06-11

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  RIDEOUT VINCENT LEO

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/32 ,  H01L21/336 ,  H01L21/762 ,  H01L21/31 ,  H01L21/76

    Abstract: A fabrication method is disclosed for providing self-aligned (i.e., misregistration tolerant or "borderless") contact vias for electrical connections between metal interconnection lines and underlying doping semiconductive regions of an integrated circuit. The described method utilizes an oxidation barrier layer material which is patterned twice to provide, first, the recessed oxide isolation regions and, later, the self-aligned contact vias. An example of an n-channel FET embodiment is described wherein self-aligned contact vias are provided between aluminum interconnection lines and n-type doped source and drain regions. In the described method, at least a portion of the normally present misregistration region or border is eliminated between the boundary of a recessed isolation oxide and the boundary of the via. The latter is ultimately coincident with the boundary of an underlying doped region. Elimination of contact borders advantageously reduces the overall area required for the contact, and consequently, reduces the overall surface area of the integrated circuit chip. Additionally, the metal step coverage at the contact edges is improved over prior art etched contact vias. The self-aligned contact via is achieved by repeated patterning of an oxidation barrier coupled with the intermediate step of thermally growing a thick insulation oxide layer over areas wherein devices such as FET's or bipolar transistors will be formed.

    5.
    发明专利
    未知

    公开(公告)号：CH594956A5

    公开(公告)日：1978-01-31

    申请号：CH670475

    申请日：1975-05-26

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  SPAMPINATO DOMINIC PATRICK

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70 ,  G11C11/34 ,  G11C5/02

    Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

    MEMORY ARRAY
    8.
    发明专利
    MEMORY ARRAY 未知

    公开(公告)号：DE3277096D1

    公开(公告)日：1987-10-01

    申请号：DE3277096

    申请日：1982-05-07

    Applicant: IBM

    Inventor： CHAO HU HUBERT ,  DENNARD ROBERT HEATH

    IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  G11C11/24 ,  G11C11/40

    Abstract: An FET dynamic RAM array has one-FET-device cells (4) each associated with a respective bit line portion, there being two bit line portions, each associated with a respective node (N2) of the sense amplifier (3) by two FET switches operated by V (TOP) and V (BOTTOM). Capacitors (6) in the cells are charged according to the information they store. Cells are accessed by raising the potential of a word line e.g. WORD n for the cell with capacitor Cn, 1. If at that time capacitor Cn+ 1, 1 stores a >, and if BIT LINE L (BOTTOM) is at ground, the drain-source voltage of the associated FET (5) may force it to conduct so that the stored information is lost. This is prevented by V (BOTTOM) turning off L (BOTTOM) while the potential on BIT LINE L (BOTTOM) is at the precharge level (approximately VDD caused by OPC. The array is single-polysilicon, in which portions of word lines are used as cell capacitor electrodes.

    9.
    发明专利
    未知

    公开(公告)号：DE2525225A1

    公开(公告)日：1976-02-05

    申请号：DE2525225

    申请日：1975-06-06

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  SPAMPINATO DOMINIC PATRICK

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70

    Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

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