公开(公告)号：EP1668672A4

公开(公告)日：2008-06-25

申请号：EP04782603

申请日：2004-08-30

Applicant: IBM

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

公开(公告)号：EP1927128A4

公开(公告)日：2009-01-28

申请号：EP06804017

申请日：2006-09-22

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

公开(公告)号：EP1676297A4

公开(公告)日：2008-06-25

申请号：EP04795693

申请日：2004-10-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/336 ,  H01L21/461 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L31/117

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

公开(公告)号：EP1676296A4

公开(公告)日：2008-08-20

申请号：EP04795664

申请日：2004-10-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

IPC: H01L29/10 ,  H01L20060101 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/778 ,  H01L31/036 ,  H01R4/64

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

公开(公告)号：EP1382064A4

公开(公告)日：2008-05-07

申请号：EP01987463

申请日：2001-12-27

Applicant: IBM

Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

IPC: H01L21/3205 ,  H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/31 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

公开(公告)号：WO02089180A3

公开(公告)日：2003-02-06

申请号：PCT/US0149571

申请日：2001-12-27

Applicant: IBM

Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners (20) of a Si-containing transistor having a gate conductor (16) and a dielectric cap (18), and exposing the transistor including implanted transistor gate corners (20) to an oxidizing ambient. The ions employed in the implant step include Si, non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

Abstract translation: 提供了一种提高晶体管栅极角氧化速率的方法，而不显着增加整体处理方案的热预算。 具体地，本发明的方法包括将离子注入到具有栅极导体（16）和电介质盖（18）的含硅晶体管的栅极拐角（20）中，并且使包括注入的晶体管栅极角（20）的晶体管暴露， 到氧化环境。 在注入步骤中使用的离子包括Si，不延迟氧化离子如O，Ge，As，B，P，In，Sb，Ga，F，Cl，He，Ar，Kr和Xe; 及其混合物。

公开(公告)号：WO2005043590A3

公开(公告)日：2006-09-21

申请号：PCT/US2004034528

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/778 ,  H01L31/036 ,  H01R4/64

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括用于pFET（40）和nFET（45）的沟道。 在nFET沟道的沟道中生长SiGe层（45a），并且在pFET沟道中生长Si：C层（40a）。 SiGe和Si：C匹配下层Si层（15）的晶格网络，以在上覆的生长的外延层（60）中产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。 在进一步的实施中，SiGe层在nFET和pFET沟道中生长。 在这种实现中，pFET通道中的应力水平应该大于3GPa。

公开(公告)号：WO2005043591A3

公开(公告)日：2007-06-21

申请号：PCT/US2004034562

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/336 ,  H01L21/461 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L31/117

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract translation: 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：WO2007038237A3

公开(公告)日：2007-07-26

申请号：PCT/US2006036916

申请日：2006-09-22

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

Abstract translation: 本发明提供一种半导体结构，其具有至少一个CMOS器件，其中米勒电容，即重叠电容，并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，并且第一栅极氧化物比第二栅极氧化物高k，反之亦然 。

公开(公告)号：WO2005043591A8

公开(公告)日：2005-11-03

申请号：PCT/US2004034562

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L20060101 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract translation: 一种半导体器件和制造半导体器件的方法。 该半导体器件包括用于pFET和nFET的沟道。 SiGe层选择性地生长在pFET沟道的源极和漏极区中，并且Si：C层选择性生长在nFET沟道的源极和漏极区中。 SiGe和Si：C层匹配下面的Si层的晶格网络以产生应力分量。 在一个实施方式中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。