3.
    发明专利
    未知

    公开(公告)号:DE4427309C2

    公开(公告)日:1999-12-02

    申请号:DE4427309

    申请日:1994-08-02

    Applicant: IBM

    Abstract: PCT No. PCT/EP95/02150 Sec. 371 Date Jan. 31, 1997 Sec. 102(e) Date Jan. 31, 1997 PCT Filed Jun. 6, 1995 PCT Pub. No. WO96/04611 PCT Pub. Date Feb. 15, 1996Described is a method for manufacturing of carrier element modules of a thin carrier element (4) and a thereon mounted semiconductor chip (2). This method renders possible the application of chips (2) with great dimensions (macro-chips) and a wide variety of different types. A chip transfer moulding process is designed so that a minimised height-without the need for reworking-is achievable, and therefore a less costly surface mounting of the chips can be applied. The manufactured module according to the invention can be used as well as in flexible circuit boards (e.g. for cameras) or in chipcards. The method according to the present invention has a first step of putting the at least one IC (2) onto the carrier element (4), a second step of contacting the at least one IC (2) with the carrier element (4) and a third step of transfer moulding a transfer moulding compound (18) to encapsulate the IC (2).

    4.
    发明专利
    未知

    公开(公告)号:DE3683763D1

    公开(公告)日:1992-03-12

    申请号:DE3683763

    申请日:1986-03-27

    Abstract: Identically positioned alignment marks are formed on opposite sides of a semiconductor wafer by (i) coating both wafer sides with an insulating layer (2,3); (ii) directing high energy heavy ions onto the front side layer (2), the ions penetrating both layers (2,3) nuclear tracks (4, 4') to form single disturbed lattice nuclear tracks (4, 4') in the layers without disturbing the crystal latt-ice of the wafer; (iii) etching the nuclear tracks (4,4') to form identically positioned pores in the layers; and (iv) using the pores as alignment marks for further processing.

Patent Agency Ranking