公开(公告)号：US3507036A

公开(公告)日：1970-04-21

申请号：US3507036D

申请日：1968-01-15

Applicant: IBM

Inventor： ANTIPOV IGOR ,  FEINBERG IRVING ,  ZANDE CHARLES H VAN DE ,  WING WAILEY L ,  BERGER HORST H

IPC: H01L23/544 ,  H01L7/02

CPC classification number: H01L22/34

公开(公告)号：US3697318A

公开(公告)日：1972-10-10

申请号：US3697318D

申请日：1969-12-12

Applicant: IBM

Inventor： FEINBERG IRVING ,  LANGDON JACK L ,  SITLER CARL L

IPC: H01L21/82 ,  H01L23/04 ,  H01L27/06 ,  H01L27/118 ,  B44D1/18 ,  H01B13/00 ,  H05K3/00

CPC classification number: H01L23/041 ,  H01L21/82 ,  H01L27/0658 ,  H01L27/118 ,  H01L2924/0002 ,  Y10S148/085 ,  Y10S148/102 ,  Y10S148/115 ,  Y10S438/975 ,  Y10T29/49133 ,  H01L2924/00

Abstract: THIS INVENTION RELATES GENERALLY TO MONOLITHIC INTEGRATED STRUCTURES INCLUDING THE FABRICATION THEREOF AND, MORE PARTICULARLY, TO A MONOLITHIC INTEGRATED STRUCTURE THAT IS USED TO PROVIDE A MULTIPLICITY OF VARIOUS CIRCUIT INTERCONNECTIONS SO AS TO PERMIT MORE THAN ONE CIRCUIT TO BE MADE FOR EACH STRUCTURE. MANY LOGIC TYPE INTEGRATED STRUCTURES CAN BE FABRICATED FROM A SINGLE MASTER SLICE CONFIGURATION WHICH CONTAINS A NUMBER OF COMPONENTS IN A PATTERN FAVORABLE TO THE FORMATION OF ANY SELECTED LOGIC CIRCUIT FROM A CLASS OF MANY SUCH CIRCUITS. ADDITIONALLY, FABRICATION TECHNIQUES ARE DESCRIBED FOR FACILITATING FORMATION OF THE INTEGRATED CHIP WHICH INCLUDE MASK ALIGNMENT TECHNIQUES, CHIP TESTING TECHNIQUES, CHIP IDENTIFICATION, PROCESS STEP IDENTIFICATION, ENGINEERING CHANGE NUMBER IDENTIFICATION, ETC.

公开(公告)号：US3539876A

公开(公告)日：1970-11-10

申请号：US3539876D

申请日：1967-05-23

Applicant: IBM

Inventor： FEINBERG IRVING ,  LANGDON JACK L ,  SITLER CARL L

IPC: H01L21/8222 ,  H01L23/04 ,  H01L27/06 ,  H01L27/118 ,  H02B1/04 ,  H05K1/16

CPC classification number: H01L27/0658 ,  H01L21/8222 ,  H01L23/041 ,  H01L27/118 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15173 ,  H01L2924/3025 ,  Y10S148/037 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/102 ,  Y10S148/162

公开(公告)号：DE3577481D1

公开(公告)日：1990-06-07

申请号：DE3577481

申请日：1985-09-10

Applicant: IBM

Inventor： CAVALIERE JOSEPH RICHARD ,  LAFAVE LAWRENCE EDWARD ,  FEINBERG IRVING ,  KRAUS CHARLES JOHN ,  MACK ALFRED ,  VALENTINE EDWARD HUBERT

IPC: G01R31/26 ,  G01R1/06 ,  G01R1/073 ,  G01R31/28

公开(公告)号：DE3071907D1

公开(公告)日：1987-03-26

申请号：DE3071907

申请日：1980-11-10

Applicant: IBM

Inventor： FEINBERG IRVING ,  WU LEON LI-HENG

IPC: H01G4/12 ,  H01G2/00 ,  H01G4/005 ,  H01G4/30 ,  H01L27/01 ,  H01G1/147

Abstract: A decoupling capacitor for highly integrated, fast switching logic circuit modules. The capacitor comprises stacked ceramic sheets having metallized surfaces. The sheets are connected together in groups. Alternate groups are connected to a first electrode. Intervening alternate groups are connected to a second electrode. The connections are all made to the same ends of all the sheets so that the current flows in opposite directions through adjacent facing plates.

公开(公告)号：DE3485816D1

公开(公告)日：1992-08-20

申请号：DE3485816

申请日：1984-11-23

Applicant: IBM

Inventor： FEINBERG IRVING ,  WU LEON LI-HENG ,  YUAN LEO

IPC: H01L21/822 ,  H01L21/8222 ,  H01L23/522 ,  H01L27/04 ,  H01L27/06 ,  H01L27/07 ,  H03K19/003 ,  H01L23/58 ,  H03K19/00

公开(公告)号：CA1182583A

公开(公告)日：1985-02-12

申请号：CA404031

申请日：1982-05-28

Applicant: IBM

Inventor： DOUGHERTY WILLIAM E ,  FEINBERG IRVING ,  HUMENIK JAMES N ,  PLATT ALAN

IPC: H01L27/04 ,  H01G2/06 ,  H01G4/06 ,  H01G4/10 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01G1/035 ,  H01G1/14

Abstract: THIN FILM DISCRETE DECOUPLING CAPACITOR A decoupling capacitor for mounting on an integrated circuit multi-layer ceramic. A bottom layer electrode, is evaporated or sputtered onto a carrier. A high dielectric layer is deposited followed by the upper metallurgy and a top isolating layer. Via holes are etched to respective electrode layers, ball limiting metalization deposited thereon followed by solder balls. The electrode is mounted onto the substrate, solder balls face down in contact with a compatible footprint.

公开(公告)号：DE1764336A1

公开(公告)日：1972-03-23

申请号：DE1764336

申请日：1968-05-18

Applicant: IBM

Inventor： FEINBERG IRVING ,  LEE LANGDON JACK ,  LEE SITLER CARL

IPC: H01L21/8222 ,  H01L23/04 ,  H01L27/06 ,  H01L27/118 ,  H01L19/00

Abstract: 1,236,404. Integrated circuits. INTERNATIONAL BUSINESS MACHINES CORP. 9 May, 1968 [23 May, 1967], No. 46663/70. Divided out of 1,236,401. Heading H1K. The disclosure is identical with that of Specification 1,236,401 from which the present application is divided but the claims relate to a semi-conductor wafer comprising a plurality of areas each including a number of devices interconnected to form a circuit, the areas being in a co-ordinate array to permit dicing by intersecting sets of cuts and each being provided with a graded mark on two of its edges to permit a visual indication of the accuracy of dicing.

公开(公告)号：DE3577967D1

公开(公告)日：1990-06-28

申请号：DE3577967

申请日：1985-06-24

Applicant: IBM

Inventor： FEINBERG IRVING ,  KRAUS CHARLES JOHN ,  STOLLER HERBERT IVAN

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/04 ,  H05K1/00 ,  H05K1/03 ,  H05K3/22 ,  H01L23/52 ,  H05K3/46

Abstract: A multiple chip module is provided with an engineering change (EC)/repair facility by means of delete lines (7', 16) located on both major surfaces of the module. In one embodiment, defective pin vias (9') through the module are repaired by use of the delete lines on both major surfaces.

公开(公告)号：GB1236402A

公开(公告)日：1971-06-23

申请号：GB4666170

申请日：1968-05-09

Applicant: IBM

Inventor： FEINBERG IRVING ,  LANGDON JACK LEE ,  SITLER CARL LEE

IPC: H01L21/8222 ,  H01L23/04 ,  H01L27/06 ,  H01L27/118

Abstract: 1,236,402. Integrated circuits. INTERNATIONAL BUSINESS MACHINES CORP. 9 May, 1968 [23 May, 1967], No. 46661/70. Divided out of 1,236,401. Heading H1K. The disclosure is identical with that of Specification 1,236,401 from which the present application is divided. The claims are to an integrated circuit comprising a semi-conductor substrate having formed therein a sufficient number of semi-conductor devices to permit of interconnection to form one of a plurality of different circuits with spare capacity, and a plurality of terminal structures spaced around the area containing the devices, the devices including a number of resistors each consisting of a region of one conductivity type located in region of opposite type common to all the resistors.