公开(公告)号：JP2000357963A

公开(公告)日：2000-12-26

申请号：JP2000118392

申请日：2000-04-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DORTU JEAN-MARC ,  CHU ALBERT M ,  FERRAIOLO FRANK

IPC: G06F1/10 ,  H03K5/14 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081

Abstract: PROBLEM TO BE SOLVED: To obtain a delay element including a delay locked loop(DLL), where a follow-up ability with respect to delay which occurs in a circuit is improved. SOLUTION: A delay locked loop circuit 100 is provided with a delay line 112, the delay element 110 and a phase comparator 114. In this case, the circuit is constituted, in such a way that the delay line 112 generates delay in accordance with a control signal and is connected to an input node and an output node, that the delay element 110 is connected to the input node, gives a prescribed delay value to an input signal from the input node and supplied the delayed input signal is supplied and that the phase comparator 114 is connected to the output node and the delay element 110, compares the phase of the output signal with that of the delayed input signal, and outputs the control signal to the delay line 112 so that the line 112 gives the prescribed delay value to a part between the input node and the output node by the control signal.

公开(公告)号：WO2009100976A3

公开(公告)日：2009-11-12

申请号：PCT/EP2009050819

申请日：2009-01-26

Applicant: IBM ,  FERRAIOLO FRANK ,  DREPS DANIEL ,  REESE ROBERT ,  SCHMATZ MARTIN

Inventor： FERRAIOLO FRANK ,  DREPS DANIEL ,  REESE ROBERT ,  SCHMATZ MARTIN

IPC: H04L25/03

CPC classification number: H04L25/03866

Abstract: A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.

Abstract translation: 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。

公开(公告)号：GB2509375A

公开(公告)日：2014-07-02

申请号：GB201319714

申请日：2013-11-08

Applicant: IBM

Inventor： HARPER HUBERT ,  DREPS DANIEL ,  FERRAIOLO FRANK ,  WEBEL TOBIAS ,  WEISS ULRICH ,  TONG CHING-LUNG L ,  MAK PAK-KIN

IPC: G06F1/12 ,  G06F1/08 ,  G06F13/40

Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency; the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.

公开(公告)号：GB2509375B

公开(公告)日：2014-12-10

申请号：GB201319714

申请日：2013-11-08

Applicant: IBM

Inventor： HARPER HUBERT ,  DREPS DANIEL ,  FERRAIOLO FRANK ,  WEBEL TOBIAS ,  WEISS ULRICH ,  TONG CHING-LUNG L ,  MAK PAK-KIN

IPC: G06F1/12 ,  G06F1/08 ,  G06F5/16 ,  G06F13/40