公开(公告)号：JPS62105467A

公开(公告)日：1987-05-15

申请号：JP25710886

申请日：1986-10-30

Applicant: IBM

Inventor： GOTH GEORGE R ,  MALAVIYA SHASHI D

IPC: H01L27/04 ,  G11C11/403 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8229 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/102 ,  H01L27/108

公开(公告)号：CA1233914A

公开(公告)日：1988-03-08

申请号：CA503286

申请日：1986-03-04

Applicant: IBM

Inventor： CSERVAK NANCY R ,  FRIBLEY SUSAN K ,  GOTH GEORGE R ,  TAKACS MARK A

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/312 ,  H01L21/762 ,  H01L21/46

Abstract: Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low density trench regions with this material. After over-filling the trenches with the polyimide and obtaining a non-planar polyimide layer having a thickness much larger in the low trench density regions than that in the high density regions, a photoresist layer is applied thereover. The photoresist is then controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask over the trenches and a thin wetting layer of photoresist over the remainder of the substrate. Next, by means of a thermal step, the blockout photoresist is caused to reflow to form a relatively thick photoresist layer over the high trench density regions and a thin photoresist layer over the low trench density regions, thereby exactly compensating for the non-planarity of the polyimide layer.

公开(公告)号：CA1139015A

公开(公告)日：1983-01-04

申请号：CA349764

申请日：1980-04-14

Applicant: IBM

Inventor： BARILE CONRAD A ,  GOTH GEORGE R ,  MAKRIS JAMES S ,  NAGARAJAN ARUNACHALA ,  RAHEJA RAJ K

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/07 ,  H01L29/417 ,  H01L21/22

Abstract: BIPOLAR TRANSISTOR FABRICATION PROCESS WITH AN ION IMPLANTED EMITTER A very high current ion implanted emitter is formed in a diffused base. Windows are made through the silicon nitride and silicon dioxide layers to both the base contact and the emitter regions using a resist mask. These regions are than protected by resist and the collector contact window is opened through the remainder of the silicon dioxide layer to the reach through region. A screen oxide is grown in all the exposed areas after removal of the resist mask. A resist mask is applied which covers only the base and Schottky anode regions. Arsenic is then implanted through the exposed screened areas followed by an etch back step to remove the top damaged layer. With some remaining screen oxide serving as a cap, the emitter drive-in is done. FI 9-78-055

公开(公告)号：CA1240411A

公开(公告)日：1988-08-09

申请号：CA529468

申请日：1987-02-11

Applicant: IBM

Inventor： GOTH GEORGE R

IPC: H01L21/22 ,  H01L21/033 ,  H01L21/28 ,  H01L21/60 ,  H01L23/52

Abstract: Disclosed is a process for forming self-aligned low resistance ohmic contact to a P doped region (e.g., base of an NPN device) in conjunction with forming similar contact to a (highly) N doped region (e.g., emitter of NPN). After forming a P doped region in an N type monocrystalline silicon body and masking it with an insulator (e.g. dual oxide-nitride) layer, the highly doped N region (hereafter, N+ region) is formed in a portion of the P doped region by selectively opening the insulator layer and introducing N dopant therethrough. This opening also serves as contact opening for the N+ region. Contact opening for the P region is formed by selectively etching the insulator layer. The structure is subjected to a low temperature steam oxidation to from an oxide layers in the P contact and N+ contact regions, the oxide in the N+ contact being about 3-5 times thicker than that in the P contact region due to the significantly higher oxidation rate of the N+ region relative to the P doped region. The oxide in the P contact is etched off while retaining a substantial portion of the oxide grown in the N+ contact region. P type dopant is then introduced into the P contact opening to achieve solid solubility limit of the P dopant species in silicon. The oxide remaining in the N+ contact region is removed and contact metallurgy is established with all contacts.

公开(公告)号：CA1191971A

公开(公告)日：1985-08-13

申请号：CA408724

申请日：1982-08-04

Applicant: IBM

Inventor： GOTH GEORGE R ,  MALAVIYA SHASHI D

IPC: H01L27/00 ,  H01L21/72

Abstract: Lateral Device Structures Using Self-Aligned Fabrication Techniques Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithograph. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

公开(公告)号：CA1166760A

公开(公告)日：1984-05-01

申请号：CA378808

申请日：1981-06-02

Applicant: IBM

Inventor： GOTH GEORGE R ,  MAGDO INGRID E ,  MALAVIYA SHASHI D

IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/70 ,  H05K3/02 ,  H01L27/02

Abstract: SELF-ALIGNED METAL PROCESS FOR INTEGRATED CIRCUIT METALLIZATION A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive FI9-80-010 ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. FI9-80-010

公开(公告)号：DE69807621T2

公开(公告)日：2003-11-27

申请号：DE69807621

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：CA1258140A

公开(公告)日：1989-08-01

申请号：CA508357

申请日：1986-05-05

Applicant: IBM

Inventor： GOTH GEORGE R

IPC: H01L21/76 ,  H01L21/762

Abstract: Disclosed is a structure having two highly and similarly doped, e.g., P+ type, regions embedded in close juxtaposition in a trench-isolated N type silicon mesa which contains the novel feature of N+ channel stops embedded in the N type mesa between the P type regions. The channel stops are self-aligned to the walls of trench to arrest charge leakage between the P type regions due to parasitic transistor action along the trench wall. The P type regions may constitute two resistors, the emitter and collector of a lateral PNP transistor, etc. The dopant concentration in the channel stops is about one to two orders of magnitude higher than that in the N type silicon. Disclosed too is a process of forming channel stops which starts with a, for example, N type silicon substrate having on the surface thereof an insulator trench mask defining the region of silicon where an isolation trench is desired. A blockout mask having an opening in correspondence with the portion of the would-be silicon mesa where a channel stop is desired is formed. N type dopant is introduced into the exposed silicon followed by an anneal step to laterally diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region. Upon forming a pair of highly P doped regions on either side of the shallow highly N doped region, the latter functions as a channel stop to arrest charge leakage between the P doped regions due to parasitic FET action at the trench walls.

公开(公告)号：CA1243421A

公开(公告)日：1988-10-18

申请号：CA532447

申请日：1987-03-19

Applicant: IBM

Inventor： GOTH GEORGE R

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732 ,  H01L21/72 ,  H01L27/04

Abstract: Disclosed is a complementary vertical NPN and PNP pair having matched performance. The PNP collector is located deep in an epitaxial layer overlying a semiconductor substrate. The junction depths and surface concentrations of both emitters are quite similar; the junction depths and surface concentrations of bases of the complementary devices are also similar to each other. The PNP and NPN emitters are provided with self-aligned conductive contacts. A high dopant concentration equal to that in the emitters is provided in all contacts of the transistor elements to reduce the contact resistances. Disclosed too is a process of forming the above structure. Starting with a semiconductor substrate having a blanket N+ NPN subcollector and an epitaxial layer thereon having first and second active regions, an NPN base precursor and PNP collector reach-through precursor are simultaneously implanted in the first and second active regions, respectively. PNP collector is then formed in the second active region by implanting P type species to lodge them at the bottom the epitaxial layer. PNP base precursor is then implanted in the surface region of the epitaxial layer in the second active region. By annealing, the the NPN and PNP bases and PNP collector reach-through are obtained from their respective precursors. A high-dopant concentration and shallow NPN emitter and low-resistance contact region for PNP base are simultaneously implanted. PNP emitter and contact regions for PNP collector reach-through and NPN base having a concentration and function depth similar to those of the NPN emitter are simultaneously implanted. Self-aligned conductive contacts are established with both emitters and all other transistor elements.

公开(公告)号：DE69807621D1

公开(公告)日：2002-10-10

申请号：DE69807621

申请日：1998-06-26

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.