公开(公告)号：EP1719181A4

公开(公告)日：2010-08-25

申请号：EP04702191

申请日：2004-01-14

Applicant: IBM

Inventor： ANGYAL MATTHEW ,  HICHRI HABIB ,  LEE JIA ,  MCHERRON DALE ,  NYE HENRY A III

IPC: H01L29/00 ,  C23C16/40 ,  C23C16/455 ,  H01L21/316

CPC classification number: H01L21/31633 ,  C23C16/401 ,  C23C16/45523 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274

公开(公告)号：JP2004193605A

公开(公告)日：2004-07-08

申请号：JP2003405153

申请日：2003-12-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DALTON TIMOTHY J ,  DAS SANJIT K ,  ENGEL BRETT H ,  HERBST BRIAN W ,  HICHRI HABIB ,  KASTENMEIER BERND E ,  MALONE KELLY ,  MARINO JEFFREY R ,  MARTIN ARTHUR ,  MCGAHAY VINCENT J ,  MELVILLE IAN D ,  NARAYAN CHANDRASEKHAR ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for reducing thermal mechanical stress in stack and via. SOLUTION: An interconnection structure for a semiconductor device comprises an organic low-k (low specific dielectric constant) dielectric layer formed on a lower metallization. The via to be formed here is in this low-k dielectric layer, and combines a lower metallization line formed on the lower metallization level and an upper metallization line formed on an upper metallization level. This via is surrounded by structure collar selected from material with CTE that can protect the via from shearing force generated after the thermal expansion of the low-k dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2011061228A

公开(公告)日：2011-03-24

申请号：JP2010247790

申请日：2010-11-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FITZSIMMONS JOHN ,  GRECO STEPHEN ,  LEE JIA ,  GATES STEPHEN ,  SPOONER TERRY ,  ANGYAL MATTHEW ,  HICHRI HABIB ,  STANDAERT THEORDORUS ,  BIERY GLENN

IPC: H01L21/768 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an advanced back-end-of-line (BEOL) interconnect structure provided with a hybrid dielectric body. SOLUTION: Inter layer dielectric body (ILD) for a via level is preferably different from an ILD for a line level. In a preferable embodiment, the ILD the via level is formed with a low-k SiCOH material, and the ILD for the line level is formed with a low-k polymer thermosetting material. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供具有混合电介质体的高级后端（BEOL）互连结构。 解决方案：用于通孔电平的层间电介质体（ILD）优选地不同于线路电平的ILD。 在优选的实施方案中，ILD通过低k SiCOH材料形成通孔层，并且用低k聚合物热固性材料形成线水平的ILD。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：AT487230T

公开(公告)日：2010-11-15

申请号：AT06778031

申请日：2006-07-27

Applicant: IBM

Inventor： HICHRI HABIB ,  LARSEN KIMBERLY ,  MAYNARD HELEN ,  PETRARCA KEVIN

IPC: H01L21/02 ,  H01F17/00 ,  H01F41/04 ,  H01F41/10 ,  H01L21/768

Abstract: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.

公开(公告)号：AU2003279460A1

公开(公告)日：2004-06-03

申请号：AU2003279460

申请日：2003-11-07

Applicant: IBM

Inventor： HICHRI HABIB ,  STANDAERT THEORDORUS ,  BIERY GLENN ,  FITZSIMMONS JOHN ,  GRECO STEPHEN ,  LEE JIA ,  GATES STEPHEN ,  SPOONER TERRY ,  ANGYAL MATTHEW

IPC: H01L21/768 ,  H01L23/532

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

公开(公告)号：DE602006018049D1

公开(公告)日：2010-12-16

申请号：DE602006018049

申请日：2006-07-27

Applicant: IBM

Inventor： HICHRI HABIB ,  LARSEN KIMBERLY ,  MAYNARD HELEN ,  PETRARCA KEVIN

IPC: H01L21/02 ,  H01F17/00 ,  H01F41/04 ,  H01F41/10 ,  H01L21/768