公开(公告)号：EP1665275A4

公开(公告)日：2008-12-24

申请号：EP04821590

申请日：2004-08-25

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/14 ,  G11C11/405 ,  G11C11/4094 ,  G11C11/4099

CPC classification number: G11C11/405 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4094 ,  G11C11/4099

Abstract: A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.

公开(公告)号：EP1920441A4

公开(公告)日：2009-04-29

申请号：EP06802479

申请日：2006-08-30

Applicant: IBM

Inventor： FREDEMAN GREGORY J ,  KIRIHATA TOSHIAKI ,  LESLIE ALAN J ,  SAFRAN JOHN M

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C17/16 ,  G11C17/165 ,  G11C29/027

Abstract: A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled silicide migratable e-fuse. Word line (WL) selection is performed by decoding logic (140) at Vdd while the bit line drive is switched between Vdd and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current patch for minimal voltage drop during fuse programming. A differential sense amplifier (120) with a programmable reference (130) is used for improved sense margins and can support an entire bit line rather than sense amplifiers (120) being provided for individual fuses.

公开(公告)号：EP0793237A3

公开(公告)日：1998-05-27

申请号：EP96306481

申请日：1996-09-06

Applicant: IBM

Inventor： KATOH DAISUKE ,  KIRIHATA TOSHIAKI ,  YOSHIBA MUNEHIRO

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4094 ,  G11C7/1006 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/005

Abstract: An improved data sense is provided for a DRAM in which each bit line pair is coupled through a pair of high-resistance pass gates 163 to a sense amp 166. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates 176. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

公开(公告)号：WO2005001839A3

公开(公告)日：2005-05-12

申请号：PCT/EP2004051148

申请日：2004-06-17

Applicant: IBM ,  IBM UK ,  WORDEMAN MATTHEW ,  BARTH JOHN ,  KIRIHATA TOSHIAKI

Inventor： WORDEMAN MATTHEW ,  BARTH JOHN ,  KIRIHATA TOSHIAKI

IPC: G11C7/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C8/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/40603 ,  G11C11/40615

Abstract: A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to'pipeline'the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-Eke cycle and access times with a smaller and more SER immune memory cell.

Abstract translation: 描述了利用单端双端口破坏性写存储器单元和本地回写缓冲器的存储架构。 每个单元都具有单独的读取和写入端口，可以从阵列中的一个字线上的单元读出数据，随后将其写回到这些单元，同时读出数组中另一个字线上的单元格。 通过实现读出放大器阵列，使得一个放大器耦合到每个读取位线，并且锁存器接收感测数据的结果并将该数据传送到写入数据线，可以“读取”和 读周期的回写阶段。 这允许来自一个周期的回写阶段与另一个周期的读出阶段同时发生。 通过扩展锁存器的操作以接受来自读出放大器或由存储器数据输入的数据，由列地址和掩码位修改，还可以管理读出和修改回写阶段 的写周期，允许它们同时发生。 该架构优选采用诸如2T或3T增益单元的非破坏性读取存储器单元，利用更小和更多的SER免疫存储器单元实现SRAM-Eke循环和访问时间。

公开(公告)号：EP1128269A8

公开(公告)日：2001-11-28

申请号：EP01301643

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

CPC classification number: G11C29/802

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state.

公开(公告)号：EP0732701A3

公开(公告)日：1998-11-25

申请号：EP96480016

申请日：1996-02-06

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WATANABE YOHJI ,  FUJII SHUSO

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/04

CPC classification number: G11C11/4094

Abstract: A fault-tolerant DRAM design minimizes current flow in the event of a cross-fail. A bit-line precharge current limiter is provided for the bit-line precharge equalizer circuit. The bit-line precharge current limiter is both simple and effective, requiring very little silicon area to implement. The current limiter provides self current-limiting for defective bit-lines, without the necessity for a reference cell.

Abstract translation: 容错DRAM设计可以在发生交叉故障时最大限度地减少电流。 为位线预充电均衡器电路提供位线预充电电流限制器。 位线预充电电流限制器既简单又有效，需要很少的硅面积来实现。 电流限制器为有缺陷的位线提供自限流，而不需要参考单元。

公开(公告)号：WO2007027607A3

公开(公告)日：2007-08-16

申请号：PCT/US2006033536

申请日：2006-08-30

Applicant: IBM ,  FREDEMAN GREGORY J ,  KIRIHATA TOSHIAKI ,  LESLIE ALAN J ,  SAFRAN JOHN M

Inventor： FREDEMAN GREGORY J ,  KIRIHATA TOSHIAKI ,  LESLIE ALAN J ,  SAFRAN JOHN M

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C17/16 ,  G11C17/165 ,  G11C29/027

Abstract: A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled silicide migratable e-fuse. Word line (WL) selection is performed by decoding logic (140) at Vdd while the bit line drive is switched between Vdd and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current patch for minimal voltage drop during fuse programming. A differential sense amplifier (120) with a programmable reference (130) is used for improved sense margins and can support an entire bit line rather than sense amplifiers (120) being provided for individual fuses.

Abstract translation: 一次性可编程只读存储器（OTPROM）在二维阵列的大规模硅化物可迁移电子保险丝中实现。 通过在Vdd处的解码逻辑（140）来执行字线（WL）选择，同时位线驱动在Vdd和较高电压Vp之间切换用于编程。 因此，OTPROM与其他技术兼容，并且可以与其他技术集成而无需成本加法器，并支持在熔丝编程期间最小化电压降的高电流补丁的优化。 具有可编程参考（130）的差分读出放大器（120）用于改善感测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器（120）。

公开(公告)号：WO2013077929A3

公开(公告)日：2013-08-15

申请号：PCT/US2012055061

申请日：2012-09-13

Applicant: IBM ,  FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/00

CPC classification number: G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

Abstract translation: 随机固有芯片ID生成采用保留失败签名。 使用测试设置生成第一和第二ID，第一设置比第二设置更严格，在包括第二ID比特串290的第一ID比特串275中创建更多失败。保留暂停时间控制保留失败次数，调整 由BIST引擎625执行，其中失败编号803,920满足预定的失败目标。 验证确认第一个ID是否包含第二个ID位串，该ID是用于认证的ID。 通过具有中间条件的第三ID来启用认证，使得第一ID包括第三ID位串，并且第三ID包括第二ID位串。 中间条件包括用于消除第一和第二ID边界附近的位不稳定问题的保护带。 中间条件在每次ID读取操作时发生变化，从而导致更安全的识别。

公开(公告)号：WO02054405A8

公开(公告)日：2002-09-06

申请号：PCT/US0147378

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/12 ,  G11C

CPC classification number: G11C7/12

Abstract: A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.

Abstract translation: 描述了具有电可控位线长度的位线的位线架构。 位线提供有根据执行存储器访问的需要选择性地耦合或解耦位线的局部位线段的开关。 具有可控位线长度的位线可以导致功耗的降低，而不需要附加的读出放大器或额外的金属层。

公开(公告)号：WO02054405A2

公开(公告)日：2002-07-11

申请号：PCT/US0147378

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/12 ,  G11C

CPC classification number: G11C7/12

Abstract: A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.

Abstract translation: 描述了具有电可控位线长度的位线的位线架构。 根据执行存储器访问的需要，位线提供有选择性地耦合或去耦合位线的局部位线段的开关。 位线长度可控的位线可以降低功耗，无需额外的读出放大器或额外的金属层。