公开(公告)号：EP1889194A4

公开(公告)日：2008-10-01

申请号：EP06760106

申请日：2006-05-18

Applicant: IBM

Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于识别连接两个元件的第一路径（40）中的单个通孔（30）的方法，确定替代路线是否可用于连接两个元件（10,20）（不同于冗余通孔 54）），并且用于将第二路径（50）插入到可用的替代路线（70）中。 第一路径（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，这种冗余路径（50）在拥塞阻止冗余通路（54）被插入邻近单个通路（30）时提供冗余。 如果可以使用于形成第二路径的所有附加通路（52）变得冗余，则该方法的实施例还包括移除单个通路（30）和任何冗余导线段（51）。

公开(公告)号：JP2007311773A

公开(公告)日：2007-11-29

申请号：JP2007101249

申请日：2007-04-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BICKFORD JEANNE P ,  BUEHLER MARKUS ,  HIBBELER JASON D ,  KOEHL JUERGEN ,  MAYNARD DANIEL N

IPC: H01L21/82 ,  H01L21/66

CPC classification number: G06F17/5077

Abstract: PROBLEM TO BE SOLVED: To provide a method which optimize router settings so as to improve IC yield, and to provide a computer program product. SOLUTION: Yield data in an IC manufacturing line are reviewed so as to identify structure-specific mechanisms that impact the IC yield. Next, with respect to each structure-specific mechanism, a structural identifier including a wire code, a tag and/or unique identifiers is established. With respect to a wire having different width, the structural identifier is established. Subsequently, the weighting factor is established for each structure-specific mechanism in such a way that a higher weighting factor is established with respect to a structure-specific mechanism including a thick wire which is the most proximate to multiple thick wires. The structural identifier and the weighting factor with respect to the spacing produced between single width lines, double width lines, and triple width lines and wires arranged on a large metal land. Then, the router settings are modified based on the structural identifier and the weighting factor so as to minimize systematic defects. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种优化路由器设置以提高IC产量并提供计算机程序产品的方法。 解决方案：审查IC生产线中的产量数据，以便识别影响IC产量的结构特异性机制。 接下来，关于每个结构特定机制，建立包括有线代码，标签和/或唯一标识符的结构标识符。 对于具有不同宽度的导线，建立了结构标识符。 随后，针对每个结构特定机构建立加权因子，使得相对于包括最接近多个粗线的粗线的结构特定机构建立较高的加权因子。 单个宽度线，双宽度线和三条宽度线之间产生的间距的结构标识符和加权因子以及排列在大金属地面上的导线。 然后，基于结构标识符和权重因子修改路由器设置，以便最小化系统缺陷。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2006125091A2

公开(公告)日：2006-11-23

申请号：PCT/US2006019257

申请日：2006-05-18

Applicant: IBM ,  BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供一种用于在连接两个元件的第一路径（40）中识别单个通孔（30）的方法，确定替代路径是否可用于连接两个元件（10,20）（除了冗余通孔 54）），并且用于将第二路径（50）插入到可用替代路线（70）中。 第一（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，当拥塞阻止冗余通路（54）相邻于单通道（30）插入时，这种冗余路径（50）提供冗余。 如果用于形成第二路径的所有附加通孔（52）可以是冗余的，则该方法的实施例还包括移除单个通孔（30）和任何冗余线段（51）。

公开(公告)号：DE602006006567D1

公开(公告)日：2009-06-10

申请号：DE602006006567

申请日：2006-05-18

Applicant: IBM

Inventor： BUEHLER MARKUS T ,  COHN JOHN M OLD JONES ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

公开(公告)号：DE60119866T2

公开(公告)日：2007-05-10

申请号：DE60119866

申请日：2001-09-08

Applicant: IBM

Inventor： MINKENBERG CYRIEL ,  LUIJTEN RONALD P ,  KOEHL JUERGEN ,  LEPPLA BERND ,  SCHUMACHER NORBERT

IPC: H04L49/111 ,  H04Q11/04

Abstract: The invention proposes a switching arrangement for transporting data packets which comprise a data packet destination information and a payload, to one or more output ports. The switching device is able to route the arriving data packets according to the data packet destination information, to at least one dedicated of the output ports. It comprises at each input port an input buffer with at least as many single input queues as there are output ports, and an input controller for each input port, serving for controlling the order of multiplexing the data packets from the input queues of the corresponding input buffer to the switching device. The total of input ports is divided up into several subsets of input ports. Each subset in the switching device has its separate output buffer for storing at addresses therein at least the payload of each data packet arriving at the input port. At least one set of as many output queues as the switching arrangement has output ports are arranged. In these output queues at least the address of each payload stored in the output buffer is stored, sorted according to the data packet destination information. The stored payload is then deliverable to its dedicated at least one output port under use of the stored addresses.

公开(公告)号：GB2457126B

公开(公告)日：2012-03-14

申请号：GB0900660

申请日：2009-01-16

Applicant: IBM

Inventor： ARP ANDREAS ,  KOEHL JUERGEN ,  SALZ PHILLIP

IPC: G06F17/50

公开(公告)号：DE60119866D1

公开(公告)日：2006-06-29

申请号：DE60119866

申请日：2001-09-08

Applicant: IBM

Inventor： MINKENBERG CYRIEL ,  LUIJTEN RONALD P ,  KOEHL JUERGEN ,  LEPPLA BERND ,  SCHUMACHER NORBERT

IPC: H04L49/111 ,  H04Q11/04

Abstract: The invention proposes a switching arrangement for transporting data packets which comprise a data packet destination information and a payload, to one or more output ports. The switching device is able to route the arriving data packets according to the data packet destination information, to at least one dedicated of the output ports. It comprises at each input port an input buffer with at least as many single input queues as there are output ports, and an input controller for each input port, serving for controlling the order of multiplexing the data packets from the input queues of the corresponding input buffer to the switching device. The total of input ports is divided up into several subsets of input ports. Each subset in the switching device has its separate output buffer for storing at addresses therein at least the payload of each data packet arriving at the input port. At least one set of as many output queues as the switching arrangement has output ports are arranged. In these output queues at least the address of each payload stored in the output buffer is stored, sorted according to the data packet destination information. The stored payload is then deliverable to its dedicated at least one output port under use of the stored addresses.

公开(公告)号：GB2469532A

公开(公告)日：2010-10-20

申请号：GB0906740

申请日：2009-04-18

Applicant: IBM

Inventor： BUEHLER MARKUS ,  EHRENREICH SEBASTIAN ,  KOEHL JUERGEN

IPC: G01R31/26 ,  G01R31/28

Abstract: A signal repowering chip 300 comprises an input 303, at least one inverter 302a-i connected in series to the input, and at least one switch 301a-i connected to a test enable signal 304, the switches are configured to allow a signal connected to the input to propagate through the inverters when the test signal is active. An output of the chip may be directly connected to the input. The chip may be configured to be connected to a second chip to form a three-dimensional integrated circuit, and may be configured to repower wiring connections on the second chip. A three-dimensional integrated circuit 100 comprises a first chip 105, the first chip comprising a default voltage layer 101a-b and a plurality of wiring layers 104; and a second chip 103, the second chip comprising at least one repeater, the repeater being connected 106, 107 to the default voltage level, The first chip may be configured to connect to the repeater on the second chip. A method of making a three-dimensional integrated circuit is also disclosed.

公开(公告)号：GB2457126A

公开(公告)日：2009-08-05

申请号：GB0900660

申请日：2009-01-16

Applicant: IBM

Inventor： ARP ANDREAS ,  KOEHL JUERGEN ,  SALZ PHILLIP

IPC: G06F17/50

Abstract: An integrated circuit design, two or more functional blocks (which may be top-level functions in a hierarchical circuit design) are interconnected with auxiliary or spare connections. The proposed integrated circuit design allows change of an existing design through introduction of logical and/or physical changes of the underlying integrated circuit in a cost-and time-efficient manner. These additional connections, wiring and re-powering resources, as part of the global routing step, may lead to changes in the optimisation and congestion of the ic design to a certain limit, but the evaluation of where to insert connections will allow changes late in the design process. The insertion assessment may include pin assignment, signal, circuit definition and timing constraints. Point to point interconnections may be arranged over multiple levels of the hierarchical design, between edges or at functional block level and may be trees to allow one to many connection.

公开(公告)号：AT430339T

公开(公告)日：2009-05-15

申请号：AT06760106

申请日：2006-05-18

Applicant: IBM

Inventor： BUEHLER MARKUS ,  COHN JOHN ,  HATHAWAY DAVID ,  HIBBELER JASON ,  KOEHL JUERGEN

IPC: G06F17/50

Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.