公开(公告)号：JP2003060085A

公开(公告)日：2003-02-28

申请号：JP2002184151

申请日：2002-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ROVEDO NIVO ,  LAM CHUNG H ,  MIH REBECCA D

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/10867

Abstract: PROBLEM TO BE SOLVED: To provide an integrated process at a low cost, with forms a logic circuit including an embedded DRAM array while still preserving the advantages of the logic circuit and a DRAM circuit to the maximum extent possible.
SOLUTION: The logic circuit including an embedded DRAM achieves process integration by simultaneously forming a strap connecting a memory cell capacitor with a pass transistor, and a buried dielectric layer isolating logic transistor sources and drains from a substrate.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了提供低成本的集成处理，形成包括嵌入式DRAM阵列的逻辑电路，同时尽可能地保持逻辑电路和DRAM电路的优点。 解决方案：包括嵌入式DRAM的逻辑电路通过同时形成将存储单元电容器与传输晶体管连接的带以及掩埋介电层隔离逻辑晶体管源和衬底的漏极来实现工艺集成。

公开(公告)号：JP2008060569A

公开(公告)日：2008-03-13

申请号：JP2007216287

申请日：2007-08-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ALEJANDRO GABRIEL SCHROTT ,  LAM CHUNG H ,  BREITWISCH MATTHEW

IPC: H01L27/105 ,  H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell etc. containing semiconductor features and a phase-change material. SOLUTION: The semiconductor feature defines a groove for dividing the semiconductor feature itself into a first electrode and a second electrode. The phase-change material at least partially fills the groove, and serves to electrically connect the first electrode with the second electrode. In response to a switching signal, added to at least one of the first and second electrodes, at least a part of phase-change material operates so that a low electrical resistance state and a high electrical resistance state are switched. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供包含半导体特征和相变材料的存储单元等。 解决方案：半导体特征限定用于将半导体特征本身分成第一电极和第二电极的凹槽。 相变材料至少部分地填充凹槽，并且用于将第一电极与第二电极电连接。 响应于切换信号，添加到第一和第二电极中的至少一个，至少一部分相变材料操作，从而切换低电阻状态和高电阻状态。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2000243938A

公开(公告)日：2000-09-08

申请号：JP2000035483

申请日：2000-02-14

Applicant: IBM

Inventor： LAM CHUNG H ,  MILES GLEN L ,  NAKOS JAMES S ,  WILLETS CHRISTA R

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To reduce the size of an NVRAM cell by allowing a cell selection circuit for selecting a cell in an array to respond to a plurality of logic gates and the logic gates to receive data being selected from the array. SOLUTION: A word line 180 is capacitively coupled to floating gates 180f and 228, and at the same time a word line 182 is capacitively coupled to floating gates 182f and 230. Then, four cells indicated by the floating gates 182f and floating gate parts 180f, 228, and 230 are allowed to share each of bit line diffusion regions 224 and 234, and a plurality of logic gates in a selection circuit for selecting the cells receive the data of a selected cell, thus reducing the size of an NVRAM cell for including in a single integrated circuit chip.

公开(公告)号：JP2008171543A

公开(公告)日：2008-07-24

申请号：JP2007336480

申请日：2007-12-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LAM CHUNG H

IPC: G11C16/02 ,  G11C11/406 ,  G11C13/00

CPC classification number: G11C11/5628 ,  G11C7/16 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3431 ,  G11C27/005 ,  G11C2211/5641

Abstract: PROBLEM TO BE SOLVED: To provide an operating procedure for offering a cost effective method to maximize the number of levels with respect to a characteristic parameter of a memory cell. SOLUTION: This procedure utilizes statistical analysis to determine a most likely binary value associated with the characteristic parameter value. In one embodiment, a receiving unit reads the values of the characteristic parameters for each memory cell in the memory cell collection including a target memory cell. A generating unit generates a probability distribution function of the characteristic parameter for each of the possible binary values for the memory cell collection. The generating unit uses the probability distribution function to determine the possible value range for the shifted value of the characteristic parameter of the target memory cell. The value of the characteristic parameter for the target memory cell is converted to a binary value for which the probability is highest. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种操作程序，用于提供相对于存储器单元的特性参数最大化级数的成本有效的方法。

解决方案：该过程利用统计分析来确定与特征参数值相关联的最可能的二进制值。 在一个实施例中，接收单元读取包括目标存储单元的存储单元集合中的​​每个存储单元的特性参数的值。 生成单元生成用于存储单元集合的每个可能二进制值的特性参数的概率分布函数。 生成单元使用概率分布函数来确定目标存储单元的特征参数的移位值的可能值范围。 目标存储单元的特性参数的值被转换为概率最高的二进制值。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008053717A

公开(公告)日：2008-03-06

申请号：JP2007214315

申请日：2007-08-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DENNIS M NEWNS ,  LIA KRUSIN-ELBAUM ,  LAM CHUNG H ,  LIU XIAO HU ,  ELMEGREEN BRUCE G ,  DOYLE JAMES P ,  TYBERG CHRISTY S

IPC: H01L21/82

CPC classification number: H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: PROBLEM TO BE SOLVED: To provide a heat-shielded low power PCM-based reprogrammable eFUSE device.
SOLUTION: An electrically re-programmable fuse (eFUSE) device for integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element along a longitudinal axis thereof, leaving both ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with both ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种基于热屏蔽低功率PCM的可重编程eFUSE设备。 解决方案：用于集成电路器件的电可重新编程保险丝（eFUSE）器件包括细长的加热器元件，围绕细长加热器元件的外表面沿其纵向轴线包围的电绝缘衬垫，留下细长的加热器元件的两端 加热元件与第一和第二加热器电极电接触。 相变材料（PCM）围绕电绝缘衬垫的外表面的一部分，热和电绝缘层围绕PCM的外表面，其中第一和第二熔丝电极与PCM的两端电接触。 PCM被封装在电绝缘衬垫，热和电绝缘层以及第一和第二熔丝电极中。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2005268802A

公开(公告)日：2005-09-29

申请号：JP2005077513

申请日：2005-03-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： STEPHEN S FURKAY ,  HENDRICK HAMANN ,  JOHNSON JEFFREY B ,  LAM CHUNG H ,  HON-SUM P WONG

IPC: G11C13/00 ,  G11C11/56 ,  H01L21/06 ,  H01L21/331 ,  H01L27/10 ,  H01L27/105 ,  H01L27/12 ,  H01L27/24 ,  H01L29/00 ,  H01L29/68 ,  H01L45/00

CPC classification number: H01L29/685 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide a memory structure in which electric characteristics are controlled by indirectly heating a phase change material. SOLUTION: A manufacturing method of a memory device of a phase change material and a phase change memory device prepared by the method thereof are included. Concretely, the phase change memory device contains a semiconductor structure, and the semiconductor structure includes a substrate where a first doped area is contained and a set of second doped areas are disposed at both ends thereof; the phase change material disposed on the first doped area; and a conductor disposed on the phase change material. The semiconductor structure is operated as a bipolar junction transistor when the phase change material is in a first phase, and the semiconductor structure is operated as a MOSFET when the phase change material is in a second phase. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过间接加热相变材料来控制电特性的存储结构。 解决方案：包括通过其方法制备的相变材料的存储器件和相变存储器件的制造方法。 具体地说，相变存储器件包含半导体结构，并且半导体结构包括其两端包含第一掺杂区的基片和一组第二掺杂区; 所述相变材料设置在所述第一掺杂区域上; 以及配置在相变材料上的导体。 当相变材料处于第一相位时，半导体结构作为双极结型晶体管工作，当相变材料处于第二相时，半导体结构作为MOSFET工作。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH10335465A

公开(公告)日：1998-12-18

申请号：JP11651698

申请日：1998-04-27

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  GEFFKEN ROBERT M ,  LAM CHUNG H ,  LEIDY ROBERT K

IPC: H01L21/82 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide an antifuse structure and method for personalizing a semiconductor device which can overcome the limitations of the prior art. SOLUTION: An antifuse 100 of the preferred embodiment comprises a two layer transformble insulator core between two electrodes 102, 104. The transformable insulator core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes 102, 104. The two layer core preferably comprises an injector layer 106 and a dielectric layer 108. The injector layer 106 preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer 106 and the dielectric layer 108 are non-conductive. When a sufficient voltage is applied, the core fuses together and becomes conductive.

公开(公告)号：DE102013214418A1

公开(公告)日：2014-02-13

申请号：DE102013214418

申请日：2013-07-24

Applicant: IBM

Inventor： LAM CHUNG H ,  LI JING ,  MONTOYE ROBERT K

IPC: G11C7/06

Abstract: Eine beispielhafte Ausführungsform ist eine Schaltung zum Ermitteln eines Binärwertes einer Speicherzelle. Die Schaltung weist Parallelkondensatoren mit unterschiedlichen Kapazitäten auf, um selektiv eine Verbindung mit der Speicherzelle herzustellen, und eine Steuereinheit, die so konfiguriert ist, dass die Parallelkondensatoren iterativ auf eine erste Spannung aufgeladen werden, bis ein ausgewählter Parallelkondensator bewirkt, dass die erste Spannung innerhalb eines vordefinierten Zeitbereiches über die Speicherzelle auf eine erste Vergleichsspannung abnimmt, auf der Grundlage des ausgewählten Parallelkondensators ein Binärwert der höchstwertigen Bits der Speicherzelle ermittelt wird, nach dem Ermitteln des Binärwertes der höchstwertigen Bits der Speicherzelle der ausgewählte Parallelkondensator auf eine zweite Spannung aufgeladen wird, und auf der Grundlage einer Abnahme der zweiten Spannung am ausgewählten Parallelkondensator über die Speicherzelle ein Binärwert der niedrigstwertigen Bits der Speicherzelle ermittelt wird.

公开(公告)号：DE112010003457T5

公开(公告)日：2012-06-14

申请号：DE112010003457

申请日：2010-07-29

Applicant: IBM

Inventor： LAM CHUNG H ,  BREITWISCH MATTHEW J

IPC: H01L21/02 ,  H01L21/302 ,  H01L21/304 ,  H01L21/321

Abstract: Ein Verfahren zur Herstellung einer Phasenwechsel-Porenspeicherzelle, welches das Bilden einer unteren Elektrode, das Bilden einer ersten dielektrischen Schicht auf der unteren Elektrode, das Bilden einer Opferschicht auf der ersten dielektrischen Schicht, das Bilden einer Isolationsschicht auf der Opferschicht und das Bilden einer zweiten dielektrischen Schicht auf der Isolationsschicht umfasst. Das Verfahren umfasst ferner das Bilden einer Durchkontaktierung, welche die untere Elektrode überlagert, wobei sich die Durchkontaktierung bis zu der Opferschicht erstreckt, das Ätzen durch die Opferschicht bis zu der ersten dielektrischen Schicht, um eine Pore zu bilden, die so definiert ist, dass sie sich durch die Opferschicht und die erste dielektrische Schicht hindurch erstreckt, das Aufbringen eines Phasenwechselmaterials auf der Opferschicht und in der Pore und das Entfernen des außerhalb der Pore gebildeten Phasenwechselmaterials, das Entfernen der Opferschicht, um die Pore frei zu legen, wobei die Pore vertikal ausgerichtet ist, und das Bilden einer oberen Elektrode über der Pore.

公开(公告)号：GB2485938B

公开(公告)日：2014-02-26

申请号：GB201203695

申请日：2010-07-29

Applicant: IBM

Inventor： BREITWISCH MATTHEW J ,  LAM CHUNG H

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/321

Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a dielectric layer on the bottom electrode, and forming a sacrificial layer on the dielectric layer. The method further includes selectively etching portions of the sacrificial layer and the dielectric layer to define a pore extending through the sacrificial layer and the dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.