中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.018 seconds)

    NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS
    1.
    发明公开
    NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS 审中-公开
    相变材料内容可寻址存储器元件不挥发存储器

    公开(公告)号：EP1908076A4

    公开(公告)日：2009-06-17

    申请号：EP06737703

    申请日：2006-03-09

    Applicant: IBM

    Inventor： HSU LOUIS L C ,  JI BRIAN L ,  LAM CHUNG HON ,  WONG HON-SUM PHILIP

    IPC: G11C11/24

    CPC classification number: G11C13/0004 ,  G11C15/046

    Abstract: A non- volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read- write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit- read-write-search-line, and a drain connected to another end of the second phase change material element.

    6.
    发明专利
    未知

    公开(公告)号：DE3580962D1

    公开(公告)日：1991-01-31

    申请号：DE3580962

    申请日：1985-09-20

    Applicant: IBM

    Inventor： KAUFFMANN BRUCE ALAN ,  LAM CHUNG HON

    IPC: G11C11/401 ,  G11C14/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00

    Abstract: A non-volatile dynamic memory cell in which the non- volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode (14A) which has dual control gates (16A, 16B) disposed thereon. Each control gate includes a layer (24A, 24B) of dual electron injector structure (DEIS) material and a polysilicon gate (16A, 16B). When writing a "0" from the volatile storage capacitor (14B) to the floating gate (14A), one of the control gates removes charge from the floating gate (14A). To write a "1", the other programming gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical. In order to minimize the adverse effects of process variations, the gate electrode (16A) of the word line device is electrically in common with one of the control gates.

    SEMICONDUCTOR MEMORY
    7.
    发明专利
    SEMICONDUCTOR MEMORY 未知

    公开(公告)号：DE3175419D1

    公开(公告)日：1986-11-06

    申请号：DE3175419

    申请日：1981-10-20

    Applicant: IBM

    Inventor： GRISE GARY DOUGLAS ,  HSIEH NING ,  KALTER HOWARD LEO ,  LAM CHUNG HON

    IPC: G11C14/00 ,  G11C11/34 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

    Abstract: A memory system, particularly an electrically alterable read only memory system which includes a semiconductor substrate (10) having a diffusion region (12) therein defining one end of a channel region (14), a control plate (22, T1), a floating plate (20) separated from the channel region by a thin dielectric layer (16) and disposed between the control plate (22) and the channel region (14) and means (T1-T3) for transferring charge to and from the floating plate (22). A control gate (32) is coupled to the channel region (14) and is located between the diffusion region (12) and the floating plate (22). The control gate (32) may be connected to a word line and the diffusion region (12) may be connected to a bit/sense line. The channel region (14) is controlled by the word line and the presence or absence of charge on the floating plate (20). Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate (20). The charge transfer means (T1, T3) includes an enhanced conduction insulator (24) and means (T1-T3) for applying appropriate voltages to the control plate (22) and to the control gate (32) to transfer charge to and from the floating plate (20) through the enhanced conduction insulator (24).

    Drift mitigation for multi-bit phase change material (PCM) memory cell.
    8.
    发明专利
    Drift mitigation for multi-bit phase change material (PCM) memory cell. 未知

    公开(公告)号：GB2498018A

    公开(公告)日：2013-07-03

    申请号：GB201214623

    申请日：2012-08-16

    Applicant: IBM

    Inventor： LI JING ,  LAM CHUNG HON

    IPC: G11C13/00 ,  G11C14/00 ,  G11C16/26

    Abstract: An RC based sensing scheme to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing scheme ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing scheme is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval (150 figure 6B) between these two points (125,130 figure 6B ) is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing scheme is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift.

    Einkristallines Phasenwechselmaterial
    9.
    发明专利
    Einkristallines Phasenwechselmaterial 未知

    公开(公告)号：DE112010003917T5

    公开(公告)日：2012-11-22

    申请号：DE112010003917

    申请日：2010-11-03

    Applicant: IBM ,  MACRONIX INT CO LTD

    Inventor： LAM CHUNG HON ,  SCHROTT ALEJANDRO G ,  CHEN CHIEH-FANG

    IPC: H01L45/00 ,  B05D5/00

    Abstract: Ein Verfahren zum Herstellen einer Phasenwechselspeicher(PCM)-Zelle beinhaltet Bilden einer dielektrischen Schicht oberhalb einer Elektrode, wobei die Elektrode ein Elektrodenmaterial umfasst; Bilden eines Durchgangslochs in der dielektrischen Schicht, sodass das Durchgangsloch bis hinunter zu der Elektrode reicht; und Wachsen eines Einkristalls eines Phasenwechselmaterials auf der Elektrode in dem Durchgangsloch. Eine Phasenwechselspeicher(PCM)-Zelle beinhaltet eine Elektrode, die ein Elektrodenmaterial umfasst; eine dielektrische Schicht oberhalb der Elektrode; ein Durchgangsloch in der dielektrischen Schicht; und einen Einkristall eines Phasenwechselmaterials angeordnet in dem Durchgangsloch, wobei der Einkristall die Elektrode am Boden des Durchgangslochs berührt.

    Triple polysilicon embedded vnram cell
    10.
    发明专利
    Triple polysilicon embedded vnram cell 未知

    公开(公告)号：GB2347016B

    公开(公告)日：2003-07-02

    申请号：GB0001002

    申请日：2000-01-18

    Applicant: IBM

    Inventor： LAM CHUNG HON ,  MILES GLEN ,  NAKOS JAMES SPIROS ,  WILLETS CHRISTA

    IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

    Abstract: A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.

Patent Agency Ranking