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    EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL
    5.
    发明申请
    EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL 审中-公开
    通过超弹性非晶态材料退火的硅碳取代固体溶液外延

    公开(公告)号：WO2007112432A3

    公开(公告)日：2009-03-26

    申请号：PCT/US2007065324

    申请日：2007-03-28

    Applicant: IBM ,  LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

    Inventor： LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

    IPC: H01L21/20 ,  H01L21/36

    CPC classification number: H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

    Abstract: Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y

    Abstract translation: 可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。 退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。 退火优选是闪光退火或激光退火。 该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。 该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

    N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME
    6.
    发明申请
    N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME 审中-公开
    包含双重压力机的N沟道MOSFET及其形成方法

    公开(公告)号：WO2007140130A3

    公开(公告)日：2009-04-09

    申请号：PCT/US2007069100

    申请日：2007-05-17

    Applicant: IBM ,  LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

    Inventor： LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

    IPC: H01L29/76

    CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

    Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

    Abstract translation: 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

    7.
    发明专利
    未知

    公开(公告)号：AT550782T

    公开(公告)日：2012-04-15

    申请号：AT07813250

    申请日：2007-07-24

    Applicant: IBM

    Inventor： CHAKRAVARTI ASHIMA ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

    IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8238

    Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

    8.
    发明专利
    未知

    公开(公告)号：BRPI0807243A2

    公开(公告)日：2014-06-17

    申请号：BRPI0807243

    申请日：2008-02-06

    Applicant: IBM

    Inventor： CHIDAMBAR-RAO DURESETI ,  LIU YAOCHENG ,  HENSON WILLIAM K

    IPC: H01L21/00

    Abstract: A method is provided for fabricating a field effect transistor ("FET") having a channel region in a semiconductor-on-insulator ("SOI") layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor ("FET") is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.

    9.
    发明专利
    未知

    公开(公告)号：AT521089T

    公开(公告)日：2011-09-15

    申请号：AT07797521

    申请日：2007-05-17

    Applicant: IBM

    Inventor： LI JINGHONG ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

    IPC: H01L29/76

    Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

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