公开(公告)号：JP2001285364A

公开(公告)日：2001-10-12

申请号：JP2001052146

申请日：2001-02-27

Applicant: IBM

Inventor： LUIJTEN RONALD P ,  COLMANT MICHEL

IPC: H04L12/70 ,  H04L12/931 ,  H04L12/935 ,  H04L12/937 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide a switching apparatus including several input ports and several output ports. SOLUTION: The input ports can be connected to each corresponding switch adaptor. Routing of data packets that arrive at the output port from the input port is controlled by at least one switch controller. A congestion controller is provided at each output port. The congestion controller generates during its operation permission information for notifying whether the switch adaptor can transmit the data packets to the output ports. For each input port, when a data packet is received at an input port during a data packet access controller s operation although its transmission is not permitted, the data packet is marked as disapproval by the data packet access controller.

公开(公告)号：JP2002141948A

公开(公告)日：2002-05-17

申请号：JP2001281049

申请日：2001-09-17

Applicant: IBM

Inventor： LUIJTEN RONALD P ,  MINKENBERG CYRIEL ,  SCHUMACHER NORBERT ,  JUERGEN KEHR ,  LEPPLA BERND

IPC: H04L12/851 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide a switching configuration to transport a data packet including data packet destination information and a payload to one output port or more. SOLUTION: Each input port 20 of a switching device 10 has an output buffer 35 that stores a payload of each data packet arrived in each input port 20 to its address. Furthermore, each input port 20 is provided with output queues whose number is the same as that of output ports 30. Each output queue stores addresses of each payload stored in the output buffer 35 and they are classified depending on data packet destination information. The stored payload can be sent to at least one of the output ports 30 under the use of the stored addresses at the point of time and pointed out by the addresses.

公开(公告)号：WO2011070506A3

公开(公告)日：2011-08-11

申请号：PCT/IB2010055626

申请日：2010-12-07

Applicant: IBM ,  HUNTER HILLERY C ,  LUIJTEN RONALD P ,  STANLEY-MARBELL PHILLIP

Inventor： HUNTER HILLERY C ,  LUIJTEN RONALD P ,  STANLEY-MARBELL PHILLIP

IPC: G06F9/50 ,  G06F9/48 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F9/4856 ,  G06F9/5033 ,  G06F2212/271

Abstract: A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first processor while executing; and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.

Abstract translation: 一种用于管理具有至少第一处理器和第二处理器的计算机化系统的处理资源的计算机实现的方法，所述处理器中的每一个可操作地互连到存储将由处理器处理的一组数据的存储器，所述方法包括：监视 在执行时由第一处理器访问的数据; 以及如果所述第二处理器与所述第一处理器之间的距离比所述监控数据更短，则指示中断所述第一处理器处的执行并且继续所述第二处理器处的所述执行。

公开(公告)号：GB2488260A

公开(公告)日：2012-08-22

申请号：GB201207124

申请日：2010-12-07

Applicant: IBM

Inventor： HUNTER HILLERY C ,  LUIJTEN RONALD P ,  STANLEY-MARBELL PHILLIP

IPC: G06F9/48 ,  G06F9/50

Abstract: A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first processor while executing; and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.

公开(公告)号：ES2253697T3

公开(公告)日：2006-06-01

申请号：ES03750726

申请日：2003-08-28

Applicant: IBM

Inventor： KNICKERBOCKER JOHN U ,  JACOBOWITZ LAWRENCE ,  LUIJTEN RONALD P ,  SHINDE SUBHASH L

IPC: G02B6/42 ,  G02B6/43

Abstract: Una estructura de montaje óptico para la conexión de una serie de áreas bidimensionales de matrices de VCSEL a un cuadro, que comprende: una matriz de VCSEL (10) que contiene dicha serie de áreas de VCSEL (15-i), estado rodeada dicha serie de áreas por una costura de adhesión metalizada (12) sobre una superficie superior de la misma; una unidad de transferencia óptica de precisión (20) que contiene una costura de adhesión (22) correspondiente sobre su parte inferior que corresponde a dicha costura de adhesión metalizada (12) sobre dicha matriz de VCSEL (10), estando dispuesta dicha costura (22) correspondiente sobre la parte inferior de un reborde (23), de manera que la alineación entre dicha matriz (10) y dicha unidad de transferencia óptica (20) es proporcionada por el reborde (23) que está adaptado para formar un borde vertical (13) de un escalón que es decapado en la parte superior de la matriz (10); y una primera serie de salientes (24) sobre una superficie superior de dicha unidad detransferencia óptica (20); conteniendo dicha unidad de transferencia óptica (20) medios de transferencia óptica (25-i) para transferir radiación emitida desde dicha serie de áreas de VCSEL (15- i), por lo que la limitación de la tolerancia para dichos medios de transferencia óptica (25-i) es 10 m, y la limitación de la tolerancia para la distancia vertical entre dichos medios de transferencia óptica (25-i) y dicha matriz de VCSEL (10) es 50 m; y un conector óptico (30) enchufable que tiene una unidad de transmisión óptica (35) insertada en una cavidad del mismo, una serie de receptáculos de interbloqueo (34) sobre una superficie inferior del mismo que coincide con dicha primera serie de salientes (24) sobre dicha superficie superior de dicha unidad de transferencia óptica (20) y una segunda serie de salientes (36) sobre una superficie superior de dicho conector óptico (30) enchufable para coincidencia con dicho cuadro.

公开(公告)号：DE69130392T2

公开(公告)日：1999-06-02

申请号：DE69130392

申请日：1991-07-10

Applicant: IBM

Inventor： LUIJTEN RONALD P ,  HEDDES MARCO

IPC: G06F12/02 ,  G06F5/06 ,  G06F12/08

Abstract: The present invention relates to the management of a large and fast memory. The memory is logically subdivided into several smaller parts called buffers. A buffer-control memory (11) having as many sections for buffer-control records as buffers exist is employed together with a buffer manager (12). The buffer manager (12) organizes and controls the buffers by keeping the corresponding buffer-control records in linked lists. A request manager (20), as part of the buffer manager (12), does or does not grant the allocation of a buffer. A stack manager (21) controls the free buffers by keeping the buffer-control records in a stack (23.1), and a FIFO manager (22) keeps the buffer-control records of allocated buffers in FIFO linked lists (23.2 - 23.n). The stack and FIFO managers (20), (21) are parts of the buffer manager (12), too.

公开(公告)号：DE112010004735B4

公开(公告)日：2017-01-26

申请号：DE112010004735

申请日：2010-12-07

Applicant: IBM

Inventor： HUNTER HILLERY C ,  LUIJTEN RONALD P ,  STANLEY-MARBELL PHILLIP

IPC: G06F9/50 ,  G06F9/48

Abstract: Ein auf einem Computer ausgeführtes Verfahren zum Verwalten der Verarbeitung von Ressourcen eines computergestützten Systems, das mindestens einen ersten Prozessor und einen zweiten Prozessor aufweist, wobei jeder der Prozessoren funktionsmäßig mit einem Speicher verbunden ist, der einen von einem Prozessor zu verarbeitenden Datensatz speichert, wobei das Verfahren Folgendes umfasst: Überwachen von Daten auf die der erste Prozessor während des Ausführens zugreift; und, wenn der zweite Prozessor weniger weit von den überwachten Daten entfernt ist als der erste Prozessor, Anweisen, einen Ablauf in dem ersten Prozessor zu unterbrechen und den Ablauf in dem zweiten Prozessor wieder aufzunehmen.

公开(公告)号：DE60120807D1

公开(公告)日：2006-08-03

申请号：DE60120807

申请日：2001-01-11

Applicant: IBM

Inventor： LUIJTEN RONALD P ,  COLMANT MICHEL

IPC: H04L49/111

Abstract: A switching device comprising several input ports and several output ports, whereby each of the input ports is connectable to a corresponding switch adapter. At least one switch controller controls the routing of incoming data packets from the input ports to the output ports. For each output port a congestion controller is arranged which in operation, generates grant information which signals whether the switch adapters are allowed to send the data packet to the output port. For each of the input ports a data packet access controller marks a data packet as non-compliant if the packet was erroneously sent from said output port.

公开(公告)号：DE60120807T2

公开(公告)日：2006-12-28

申请号：DE60120807

申请日：2001-01-11

Applicant: IBM

Inventor： LUIJTEN RONALD P ,  COLMANT MICHEL

IPC: H04L49/111

Abstract: A switching device comprising several input ports and several output ports, whereby each of the input ports is connectable to a corresponding switch adapter. At least one switch controller controls the routing of incoming data packets from the input ports to the output ports. For each output port a congestion controller is arranged which in operation, generates grant information which signals whether the switch adapters are allowed to send the data packet to the output port. For each of the input ports a data packet access controller marks a data packet as non-compliant if the packet was erroneously sent from said output port.

公开(公告)号：AT338439T

公开(公告)日：2006-09-15

申请号：AT02700516

申请日：2002-02-25

Applicant: IBM

Inventor： BENNER ALAN F ,  ENGBERSEN ANTONIUS ,  GOLDRIAN GOTTFRIED A ,  LUIJTEN RONALD P

IPC: H04Q11/04

Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.