公开(公告)号：DE3279917D1

公开(公告)日：1989-10-05

申请号：DE3279917

申请日：1982-06-15

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  MAUER IV JOHN LESTER ,  SARKARY HOMI GUSTADJI

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/306

Abstract: The method comprises blanket depositing a layer of a first material on a semiconductor structure, on the surface of which protruding regions (34A) have been formed bordering with a vertical wall (40) on adjacent areas, and subsequently removing completely or selectively that layer by reactive ion etching where prior to the deposition of said layer the vertical wall (40) is reshaped either by removing material from that wall (40) or by accumulating a second material on said wall (40). The method prevents that uncontrolled residues of materials like a doped polysilicon after reactive ion etching steps. These residues might be detrimental to devices and elements, like transistors and resistors formed in the semi-conductor substrate.

公开(公告)号：DE3175779D1

公开(公告)日：1987-02-05

申请号：DE3175779

申请日：1981-08-05

Applicant: IBM

Inventor： LOGAN JOSEPH SKINNER ,  MAUER IV JOHN LESTER ,  ROTHMAN LAURA BETH ,  SCHWARTZ GERALDINE COGIN ,  STANDLEY CHARLES LAMBERT

IPC: H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/52 ,  H01L21/90 ,  H01L23/54

公开(公告)号：DE3277955D1

公开(公告)日：1988-02-11

申请号：DE3277955

申请日：1982-04-27

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD ,  MAUER IV JOHN LESTER

IPC: H01L29/47 ,  H01L29/872 ,  H01L29/91

公开(公告)号：DE3279524D1

公开(公告)日：1989-04-13

申请号：DE3279524

申请日：1982-08-10

Applicant: IBM

Inventor： JOY RICHARD CARLETON ,  KEMLAGE BERNARD MICHAEL ,  MAUER IV JOHN LESTER

IPC: H01L21/822 ,  H01L21/302 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L23/52 ,  H01L27/04 ,  H01L29/73

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (14) at and just below the surface of the integrated circuit and a deep portion (30) which extends through the recessed dielectric portion (14) and extends further into the monocrystalline silicon body (2, 4) than the recessed portion. A highly doped polycrystalline silicon substrate contact (30) is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

公开(公告)号：DE3279525D1

公开(公告)日：1989-04-13

申请号：DE3279525

申请日：1982-08-10

Applicant: IBM

Inventor： JOY RICHARD CARLETON ,  KEMLAGE BERNARD MICHAEL ,  MAUER IV JOHN LESTER

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L27/04 ,  H01L29/73

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (22, 24) at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact (20) is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.