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Patent Agency Ranking1.发明申请PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS 审中-公开用于制造MOSFET器件封装，硅化物源和漏极结的工艺
公开(公告)号：WO0227799A3
公开(公告)日：2002-11-21
申请号：PCT/GB0104154
申请日：2001-09-17
IPC: H01L21/28 , H01L21/336 , H01L29/78
CPC classification number: H01L29/66545 , Y10S438/926
Abstract: A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
Abstract translation: 利用大马士革栅极工艺提供了具有最小多晶硅耗尽，硅化源极和漏极结以及非常低的薄层电阻多晶硅栅极的0.1微米以下的MOSFET器件，其中源极和漏极注入激活退火和硅化在 伪栅极区，其后被去除并被多晶硅栅极区域替代。
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2.发明专利
公开(公告)号：AU8787701A
公开(公告)日：2002-04-08
申请号：AU8787701
申请日：2001-09-17
Applicant: IBM
Inventor： BRODSKY STEPHEN BRUCE , HANAFI HUSSEIN IBRAHIM , ROY RONNEN ANDREW
IPC: H01L21/28 , H01L21/336 , H01L29/78 , H01L29/00
Abstract: A sub-0.1 mum MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
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公开(公告)号：AT314729T
公开(公告)日：2006-01-15
申请号：AT01967502
申请日：2001-09-17
Applicant: IBM
IPC: H01L21/28 , H01L21/336 , H01L29/78
Abstract: A sub-0.1 mum MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
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