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    INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS
    1.
    发明公开
    INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS 审中-公开
    连接结构与改进的电性能迁移集成电路的

    公开(公告)号：EP2283515A4

    公开(公告)日：2014-10-22

    申请号：EP09759016

    申请日：2009-05-22

    Applicant: IBM

    Inventor： FILIPPI RONALD ,  CHANDRA KAUSHIK ,  SANKARAN SUJATHA ,  HU CHAO-KUN ,  STANDAERT THEODORUS ,  GRUNOW STEPHAN ,  SIMON ANDREW H

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

    3.
    发明专利
    未知

    公开(公告)号：AT504084T

    公开(公告)日：2011-04-15

    申请号：AT06778036

    申请日：2006-07-27

    Applicant: IBM

    Inventor： BREARLEY WILLIAM ,  GRECO STEPHEN ,  SANKARAN SUJATHA ,  STANDAERT THEODORUS

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.

    4.
    发明专利
    未知

    公开(公告)号：AT463046T

    公开(公告)日：2010-04-15

    申请号：AT06760152

    申请日：2006-05-19

    Applicant: IBM

    Inventor： GRECO STEPHEN ,  STANDAERT THEODORUS

    IPC: H01L21/768 ,  H01L23/528

    Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.

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