公开(公告)号：EP2433303A4

公开(公告)日：2014-09-17

申请号：EP09845033

申请日：2009-05-22

Applicant: IBM

Inventor： FILIPPI RONALD ,  STANDAERT THEODORUS E ,  GRUNOW STEPHAN ,  SANKARAN SUJATHA ,  CHANDA KAUSHIK ,  GAMBINO JEFFREY P ,  SIMON ANDREW H ,  HU CHAO-KUN ,  BONILLA GRISELDA

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2283515A4

公开(公告)日：2014-10-22

申请号：EP09759016

申请日：2009-05-22

Applicant: IBM

Inventor： FILIPPI RONALD ,  CHANDRA KAUSHIK ,  SANKARAN SUJATHA ,  HU CHAO-KUN ,  STANDAERT THEODORUS ,  GRUNOW STEPHAN ,  SIMON ANDREW H

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

公开(公告)号：WO2012134801A3

公开(公告)日：2013-01-03

申请号：PCT/US2012028847

申请日：2012-03-13

Applicant: IBM ,  FILIPPI RONALD G ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  WANG PING-CHUAN

Inventor： FILIPPI RONALD G ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  WANG PING-CHUAN

IPC: H01L23/62 ,  H01L21/82

CPC classification number: H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A back end of the line (BEOL) fuse structure having a stack of vias (122, 132). The stacking of vias (122, 132) leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner (124) and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Abstract translation: 具有堆叠通孔（122,132）的线（BEOL）熔丝结构的后端。 通孔（122,132）的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬垫（124）和种子层的弱点导致较高的电迁移（EM）故障概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔断器编程之后损坏区域的程度，并防止损坏的介质区域的进一步传播。

公开(公告)号：GB2512009A

公开(公告)日：2014-09-17

申请号：GB201412533

申请日：2013-01-10

Applicant: IBM

Inventor： BAO JUNJING ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  CHOI SAMUEL S ,  FILIPPI RONALD G ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  MOY DAN ,  SIMON ANDREW H

IPC: H01L21/768 ,  H01L23/525

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

公开(公告)号：DE112012001490T5

公开(公告)日：2013-12-24

申请号：DE112012001490

申请日：2012-03-13

Applicant: IBM

Inventor： SIMON ANDREW H ,  CHANDA KAUSHIK ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  FILIPPI RONALD G ,  BONILLA GRISELDA ,  WANG PING-CHUAN

IPC: H01L23/62 ,  G01R31/74 ,  H01L21/82

Abstract: Eine Back-End-Of-The-Line(BEOL)-Sicherungsstruktur, die einen Stapel von Durchkontakten (122, 132) aufweist. Das Stapeln von Durchkontakten (122, 132) führt zu hohen Aspektverhältnissen, was die Überzugsschicht- und Kristallkeimbedeckung im Inneren der Durchkontakte schlechter macht. Die Schwachstellen der Überzugsschicht (124) und der Kristallkeimschichten führt zu einer höheren Wahrscheinlichkeit für einen Elektromigrations(EM)-Ausfall. Die Sicherungsstruktur geht Ausfälle aufgrund einer schlechten Überzugsschicht- und Kristallkeimbedeckung an. Entwurfsmerkmale erlauben eine Bestimmung, ob Ausfälle auftreten, eine Bestimmung des Ausmaßes des geschädigten Bereichs nach einem Programmieren der Sicherung und eine Verhinderung einer weiteren Ausbreitung des geschädigten dielektrischen Bereichs.

公开(公告)号：DE112013000362T5

公开(公告)日：2014-10-02

申请号：DE112013000362

申请日：2013-01-10

Applicant: IBM

Inventor： BONILLA GRISELDA ,  CHANDA KAUSHIK ,  CHOI SAMUEL S ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  MOY DAN ,  SIMON ANDREW H ,  BAO JUNJING ,  FILIPPI RONALD G

IPC: H01L21/82 ,  H01L23/62

Abstract: Es wird eine BEOL-E-Sicherung offenbart, die zuverlässig im Durchkontakt durchbrennt und selbst in den BEOL-Schichten mit engsten Abständen gebildet werden kann. Die BEOL-E-Sicherung kann mit einem Line-First-Dual-Damascene-Prozess gebildet werden, um einen sublithografischen Durchkontakt zu ergeben, der das programmierbare Element der E-Sicherung ist. Der sublithografische Durchkontakt kann durch Standard-Lithografie strukturiert werden, und der Querschnitt des Durchkontakts kann dem Sollprogrammierstrom entsprechend abgestimmt werden.

公开(公告)号：GB2512009B

公开(公告)日：2015-02-25

申请号：GB201412533

申请日：2013-01-10

Applicant: IBM

Inventor： BAO JUNJING ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  CHOI SAMUEL S ,  FILIPPI RONALD G ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  MOY DAN ,  SIMON ANDREW H

IPC: H01L21/768 ,  H01L23/525

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

公开(公告)号：SG159452A1

公开(公告)日：2010-03-30

申请号：SG2009051111

申请日：2009-07-30

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： BONILLA GRISELDA ,  TIEN CHENG ,  CLEVENGER LAWRENCE A ,  GRUNOW STEPHAN ,  CHAO-KUN HU ,  QUON ROGER A ,  ZHIGUO SUN ,  WEI-TSUI TSENG ,  YIHENG XU ,  YUN WANG ,  SANG OH HYEOK

Abstract: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiWCXNYHZ disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiWCXNYHZ disposed upon the second capping layer, wherein a + b + c + d = 1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w + x + y + z = 1.0 and w, x, y, and z are each greater than 0 and less than 1.