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    OUTPUT DRIVING CIRCUIT
    1.
    发明专利
    OUTPUT DRIVING CIRCUIT 失效

    公开(公告)号：JPH04291091A

    公开(公告)日：1992-10-15

    申请号：JP29253491

    申请日：1991-10-11

    Applicant: IBM

    Inventor： SANGU FUU DONGU ,  UEI WANGU ,  HIYUN JIYONGU SHIN

    IPC: G11C11/409 ,  G11C11/407 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094

    Abstract: PURPOSE: To prevent the chip area of DRAM from being considerably reduced through the use of an output driving circuit which does not need two PMOS pull-up transistors which are stacked for interfacing low on chip power voltage against off chip bus voltage. CONSTITUTION: An on-chip pump circuit generates voltage required at the time of interfacing an external bus in a first execution example. In a second execution example, external bus voltage is detected and external bus voltage is compared with on-chip VDD at the time of a try state. A third execution example is the combination of the first and second execution examples. The external bus is compared with VDD in the second execution example. Voltage higher than VDD is generated in the on-chip as in the first execution example. Voltage generated in the pertinent on-chip is used for controlling the PMOS pull-up device when bus voltage is higher than VDD instead of bus voltage.

    RETURN-TYPE BIT LINE STRUCUTRE AND ITS MANUFACTURE
    4.
    发明专利
    RETURN-TYPE BIT LINE STRUCUTRE AND ITS MANUFACTURE 失效

    公开(公告)号：JPH05218348A

    公开(公告)日：1993-08-27

    申请号：JP28689292

    申请日：1992-10-01

    Applicant: IBM

    Inventor： SAN FUU DONGU ,  UEI WANGU

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

    Abstract: PURPOSE: To reduce a parasitic capacitance and to eliminate noise by forming a pair of bit lines of a first set on a first insulating layer by forming a pair of bit lines of a second set to pile a second insulating layer on the first insulating layer for offsetting in a lateral direction and by making each to comprise mutually connecting layers. CONSTITUTION: First conductive first plural conductive bit-line pairs 32 and 32' which extend to a first direction are arranged on a first insulating layer of a substrate, having plural drain-junction regions with intervals in a surface. First and second conductive second plural conductive bit-line pairs 34 and 34' are arranged offset, in a lateral direction on a second layer arranged thereon. A first plural electrical conductive contact means which extend from a first selected drain-junction region to the first bit line 32 and a second plural electrical conductive contact means, which extends from a second selected drain- junction region to the second bit-line 34', are provided.

    WORD-LINE DRIVING CIRCUIT
    5.
    发明专利
    WORD-LINE DRIVING CIRCUIT 失效

    公开(公告)号：JPH04278285A

    公开(公告)日：1992-10-02

    申请号：JP32818191

    申请日：1991-11-15

    Applicant: IBM

    Inventor： GARII BERA BURONAA ,  SAN HOO DON ,  UEI WANGU

    IPC: G11C11/407 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    Abstract: PURPOSE: To shorten access time by driving a word line with a circuit maintaining the gate of an access transistor to negative potential through the use of DRAM using a word driving circuit reducing the word line to negative potential. CONSTITUTION: The voltage of the word line 10 is raised by using a constant negative voltage generation circuit 26 and a trench capacitor 25. Negative potential generated on a chip by the circuit 26 is stored in a capacitor 25 having capacitance which is considerably larger than that of the line 10. The word line driving circuit is constituted of an NMOS reducing transistor Tr24 and a PMOS raising Tr23. When negative potential is supplied to the source of 24, negative potential is supplied to the line 10 when Tr24 is gated to a conductive state since Tr is switched. Then, Tr23 is connected to the drain of Tr24 in series and the line 10 can be driven in a positive direction.

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