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    ELECTRONIC MODULE AND ITS PREPARATION
    2.
    发明专利
    ELECTRONIC MODULE AND ITS PREPARATION 失效

    公开(公告)号：JPH0878617A

    公开(公告)日：1996-03-22

    申请号：JP20570195

    申请日：1995-08-11

    Applicant: IBM

    Inventor： COCKERILL MARTHA A C ,  MALTABES JOHN G ,  O'CONNOR LORETTA J ,  VOLDMAN STEVEN HOWARD

    IPC: H01L25/00 ,  H01L21/66 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    Abstract: PROBLEM TO BE SOLVED: To form a monolithic electronic module by a method, wherein a plurality of planers and arrays, having a plurality of integrated circuit chips, are formed, and the planers and the arrays are stacked. SOLUTION: After a dicing pattern, which positions each array on a wafer, is determined, transfer metal 15 is adhered on a wafer. The wafer is diced along cutting grooves 17 in accordance with the dicing pattern, and a plane and a array of IC chips are formed. The IC chip, the planer and the array are protected by an insulating material, and a bonding agent is applied to the surface of the insulating material. The array of an integrated circuit chip is connected to the rear surface of the next array. In this way, a monolithic electronic module can be formed by adhering each array to the adjacent array.

    MULTICHIP SEMICONDUCTOR STRUCTURE WITH INTEGRATED CIRCUIT AND ITS PREPARATION
    4.
    发明专利
    MULTICHIP SEMICONDUCTOR STRUCTURE WITH INTEGRATED CIRCUIT AND ITS PREPARATION 失效

    公开(公告)号：JPH0992781A

    公开(公告)日：1997-04-04

    申请号：JP3173596

    申请日：1996-02-20

    Applicant: IBM

    Inventor： VOLDMAN STEVEN HOWARD ,  BAKEMAN PAUL EVANS JR

    IPC: H01L25/00 ,  G11C5/00 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide a multichip semiconductor structure having an integrated circuit and a programmable circuit which protects the input-output nodes of chips from static discharge by providing the chips of a first semiconductor device and a second semiconductor chip electrically and mechanically coupled with each other in the multichip semiconductor structure. SOLUTION: A multichip semiconductor structure is provided with a first semiconductor chip having a first circuit which gives a prescribed circuit function and a second semiconductor chip which is electrically and mechanically coupled with the semiconductor chip. The second semiconductor chip has a second circuit which partially gives a circuit function to the first circuits. That is, a memory array chip 10 is provided wit memory arrays 12 which are divided from each other by a word decoder 14 for a word line having a tap at the center. The bit switch, sense amplifier, and driver 16 of the memory array 12 are arranged along the edge section 18 of the chip 10. The circuit 14 and driver 16 are called 'memory access circuits'.

    STRUCTURE OF MULTICHIP SEMICONDUCTOR OF INTER-CHIP ELECTROSTATIC DISCHARGE PREVENTING TYPE, AND ITS MANUFACTURE
    5.
    发明专利
    STRUCTURE OF MULTICHIP SEMICONDUCTOR OF INTER-CHIP ELECTROSTATIC DISCHARGE PREVENTING TYPE, AND ITS MANUFACTURE 失效

    公开(公告)号：JPH08250643A

    公开(公告)日：1996-09-27

    申请号：JP3153796

    申请日：1996-02-20

    Applicant: IBM

    Inventor： VOLDMAN STEVEN HOWARD ,  BAKEMAN PAUL EVANS JR

    IPC: H01L25/00 ,  H01L23/528 ,  H01L23/60 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    Abstract: PROBLEM TO BE SOLVED: To protect an inter-chip electrostatic discharge preventive multi-chip semiconductor structure from electrostatic discharge or the other excessive voltage which can damage the structure by a method, wherein first and second semiconductor device chips are laminated in such a way that the chips are provided in parallel to each other and the structure is provided with a discharge suppression means for coupling electrically both chips with each other. SOLUTION: A first power surface 10 of a chip (k) is coupled electrically with the second power surface 12 of a chip (t) via an inter-chip discharge suppression network Sii . A third power surface 14 of the chip (K) is coupled electrically with a fourth power surface 16 of the chip (t) via a second inter-chip discharge suppression network Sjj . A network 20 of the chip (k) is coupled between the surfaces 10 and 14, while the suppression network 20 of the chip (t) is coupled between the surfaces 12 and 16. By such inter-chip discharge suppression networks and the discharge suppression networks in the chips, discharge which is generated between the semiconductor device chips in a multi-chip stack, between a power supply surface and an external connection point, between an external connection point and a power supply surface and between the external connection points, can be suppressed.

    6.
    发明专利
    未知

    公开(公告)号：DE69615456T2

    公开(公告)日：2002-05-02

    申请号：DE69615456

    申请日：1996-05-24

    Applicant: IBM

    Inventor： HUGHBANKS TIMOTHY SCOTT ,  ROBERTSON NEIL LESLIE ,  VOLDMAN STEVEN HOWARD ,  WALLASH ALBERT JOHN

    IPC: G11B5/10 ,  G11B5/11 ,  G11B5/31 ,  G11B5/39 ,  G11B5/40 ,  G11B5/596 ,  G11B5/00 ,  G11B19/04

    Abstract: A magneto-resistive read head (107) having a "parasitic shield" (124) provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head (107). The parasitic shield (124) is provided in close proximity to a conventional magnetic shield (113, 115). The electrical potential of parasitic shield (124) is held essentially equal to the electrical potential of the sensor element (111). If charges accumulate on the conventional shield (113, 115), current will flow to the parasitic shield (124) at a lower potential than would be required for current to flow between the conventional shield (113, 115) and the sensor element (111). Alternatively, conductive spark gap devices (203, 206) are electrically coupled to sensor element leads and to each magnetic shield (201, 202). Each spark gap (203, 206) device is brought within very close proximity of the substrate (207) to provide an alternative path for charge that builds up between the sensor element (213) and the substrate (207) to be discharged. The ends of the spark gaps (203, 206) that are brought into close proximity of the substrate are preferably configured with high electric field density inducing structures which reduce the voltage required to cause a sparkover between the spark gap device (203, 206) and the substrate (207).

    8.
    发明专利
    未知

    公开(公告)号：DE69615456D1

    公开(公告)日：2001-10-31

    申请号：DE69615456

    申请日：1996-05-24

    Applicant: IBM

    Inventor： HUGHBANKS TIMOTHY SCOTT ,  ROBERTSON NEIL LESLIE ,  VOLDMAN STEVEN HOWARD ,  WALLASH ALBERT JOHN

    IPC: G11B5/10 ,  G11B5/11 ,  G11B5/31 ,  G11B5/39 ,  G11B5/40 ,  G11B5/596 ,  G11B5/00 ,  G11B19/04

    Abstract: A magneto-resistive read head (107) having a "parasitic shield" (124) provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head (107). The parasitic shield (124) is provided in close proximity to a conventional magnetic shield (113, 115). The electrical potential of parasitic shield (124) is held essentially equal to the electrical potential of the sensor element (111). If charges accumulate on the conventional shield (113, 115), current will flow to the parasitic shield (124) at a lower potential than would be required for current to flow between the conventional shield (113, 115) and the sensor element (111). Alternatively, conductive spark gap devices (203, 206) are electrically coupled to sensor element leads and to each magnetic shield (201, 202). Each spark gap (203, 206) device is brought within very close proximity of the substrate (207) to provide an alternative path for charge that builds up between the sensor element (213) and the substrate (207) to be discharged. The ends of the spark gaps (203, 206) that are brought into close proximity of the substrate are preferably configured with high electric field density inducing structures which reduce the voltage required to cause a sparkover between the spark gap device (203, 206) and the substrate (207).

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