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    Residue calculation in modulo system using 4:2 counter
    6.
    发明专利
    Residue calculation in modulo system using 4:2 counter 未知

    公开(公告)号：GB2456406A

    公开(公告)日：2009-07-22

    申请号：GB0822762

    申请日：2008-12-15

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  FLEISCHER BRUCE MARTIN ,  HAESS JUERGEN ,  TRONG SON DAO ,  SCHWARZ ERIC MARK ,  WETTER HOLGER

    IPC: G06F7/72

    Abstract: A residue of an operand with a width of n bits with respect to a modulo m where m=2b-1, can be calculated by partitioning the operand into segments, each of b bits starting with the Least Significant Bit (LSB). The segments are applied to a counter reduction tree (21) comprising levels (22, 23) of adders (24) The adders (24) of a first level (22) below an operand register (25) with successive registers keeping the successive bit positions of the operand are 4:2 counters (24) having four inputs (In1, In2, In3, In4) plus a propagate input (44), a carry and a sum output (45, 46) plus a propagate output (43) each. the first level (22) are grouped in fours, such that the propagate outputs (43) are ring like connected with the propagate inputs (44), and that the first to fourth inputs (In1, In2, In3, In4) of the counters (24) are connected with successive registers of said operand register (25) such that first inputs (In4) of the counters (24) are connected with four successive registers in ascending order followed by second (In3), third (In2) and fourth inputs (In1), wherein a decoding is performed only one time at the end of the counter tree (21) and thus at the end of the residue generation process. This leads to a reduction in the area needed on the chip to make the calculation, relaxes the timing requirement, as the calculation requires fewer logical levels, and increases the error detection rate for a single random type of operation.

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