公开(公告)号：JPH10308363A

公开(公告)日：1998-11-17

申请号：JP11252698

申请日：1998-04-22

Applicant: IBM ,  TOSHIBA CORP

Inventor： USUI TAKAMASA ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  FILIPPI RONALD G ,  YANG CHI-HUA ,  KATADA TOMIO ,  AOCHI HIDEAKI

IPC: C23C14/14 ,  C23C14/34 ,  C23C16/06 ,  C23C28/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a manufacture of a metalization structure having a superior electrical mobility, highly textured, and suitable for electrical connection or wiring. SOLUTION: The manufacture of a metalization structure comprises depositing a first lower layer 13 made of IVA family metal such as titan and having a thickness of approximately 90 Å to 110 Å on a substrate and after which, electrical depositing a layer made of at least one element selected from a group consisting of aluminum and aluminum alloy deposited on the layer 13 in such a way as to be in ohmic contact with the layer 13.

公开(公告)号：JPH10308362A

公开(公告)日：1998-11-17

申请号：JP11245598

申请日：1998-04-22

Applicant: IBM ,  TOSHIBA CORP

Inventor： USUI TAKAMASA ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  FILIPPI RONALD G

IPC: C23C14/14 ,  C23C16/06 ,  C23C28/02 ,  H01L21/28 ,  H01L21/285

Abstract: PROBLEM TO BE SOLVED: To provide a metallization structure, which is small in resistivity, has excellent electricity transfer characteristics and at the same time, is textured to a high degree, and moreover, to prevent the formation of a hillock on the structure by a method wherein aluminium layers, aluminium alloy layers or both layers of the aluminium layers and the aluminum alloy layers, which come into contact electrically with tower group IVA metal layers having a thickness in a specified range, are formed. SOLUTION: Four or five-layer interconnected metallized layers are formed on interlayer stud connection layers 10, which are encircled with an insulator 8 and are connected with a silicon substratelike device substrate 6. Lower group IVA metal layers 13 consist of a titanium layer and the thickness of a metallization structure is about 90 to about 110 angstroms. By limiting this thickness, the structure of a metal layer, which is added afterwards, and the texture of the metal layer are controlled. Layers 15 to come into contact electrically with the lower layers 13 are aluminium layers or aluminium alloy layers. Titanium nitride layers 14 on the lower layers 13 prevent a reaction of the aluminium layers 15 with the lower layers 13 and capping layers consisting of titanium layers 18 and titanium nitride layers 19 perform an antireflection action.

公开(公告)号：EP1908105A4

公开(公告)日：2012-08-22

申请号：EP06749575

申请日：2006-04-07

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  GORDON MICHAEL S ,  RODBELL KENNETH P

IPC: H01L23/556 ,  H01L23/485

CPC classification number: H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

公开(公告)号：EP2100241A4

公开(公告)日：2011-01-12

申请号：EP07865741

申请日：2007-12-17

Applicant: IBM

Inventor： FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/16

公开(公告)号：EP1540276A4

公开(公告)日：2006-08-23

申请号：EP03793095

申请日：2003-08-15

Applicant: HYPERNEX INC ,  IBM

Inventor： KOZACZEK KRZYSZTOF J ,  KURTZ DAVID S ,  MORAN PAUL R ,  MARTIN ROGER I ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  MALHOTRA SANDRA G

IPC: G01B15/02 ,  G01N23/20 ,  G01N23/223

CPC classification number: G01N23/20 ,  G01B15/02

Abstract: An apparatus and method for mapping film thickness of one or more textured polycrystalline thin films. Multiple sample films of known thickness are provided. Each sample film is irradiated by x-ray at a measurement point to generate a diffraction image that captures a plurality of diffraction arcs. Texture information (i.e., pole densities) of the sample film is calculated based on incomplete pole figures collected on the diffraction image and used to correct the x-ray diffraction intensities from such sample. The corrected diffraction intensities are integrated for each sample film, and then used for constructing a calibration curve that correlates diffraction intensities with respective known film thickness of the sample films. The film thickness of a textured polycrystalline thin film of unknown thickness can therefore be mapped on such calibration curve, using a corrected and integrated diffraction intensity obtained for such thin film of unknown thickness.

公开(公告)号：EP1800335A4

公开(公告)日：2008-01-02

申请号：EP05797431

申请日：2005-09-20

Applicant: IBM

Inventor： PETRARCA KEVIN S ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL ,  RODBELL KENNETH P

IPC: H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76877

Abstract: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer (440). The impure copper seed layer (440) covers a barrier layer (230), which covers an insulating layer (115) that has an opening. Electroplated copper fills the opening in the insulating layer (115). Through a chemical mechanical polish, the barrier layer (230), the impure copper seed layer (440) derived from an electroplated copper bath, and the electroplated copper are planarized to the insulating layer (115).

公开(公告)号：EP1299210A4

公开(公告)日：2004-11-17

申请号：EP01952272

申请日：2001-06-27

Applicant: IBM ,  FREUDENBERG NON WOVENS

Inventor： CHEN SHYNG-TSONG ,  CHUNG ALEX SIU KEUNG ,  DAVIS KENNETH M ,  HSU OSCAR KAI CHI ,  RODBELL KENNETH P

IPC: B24B37/26 ,  B24D13/14 ,  H01L21/304 ,  B24B1/00 ,  B23C3/28 ,  B24B37/04 ,  B24D18/00 ,  B26D7/01

CPC classification number: B24B37/26 ,  Y10T409/303808 ,  Y10T409/306608 ,  Y10T409/308624

Abstract: Grooves (70, 76, 78, & 80-82) are formed in a CMP pad (12) by positioning the pad (12) on a supporting surface (10) with a working surface (22) of the pad (12) in spaced relation opposite to a router bit (24) and at least one projecting stop member (33) adjacent to the router bit (24), an outer end portion of the bit (24) projecting beyond the stop (33). When the bit (24) is rotated, relative axial movement between the bit (24) and the pad (12) causes the outer end portion of the bit (24) to cut an initial recess in the pad (12). Relative lateral movement between the rotating bit (24) and the pad (12) then forms a groove (70) which extends laterally away from the recess and has a depth substantially the same as that of the recess. The depths of the initial recess and the groove (70) are limited by applying a vacuum to the working surface (22) of the pad (12) to keep it in contact with the stop member(s) (33). Different lateral movements between the bit (24) and the pad (12) are used to form a variety of groove patterns (76, 78, & 80-82), the depths of which are precisely controlled by the stop member(s) (33).

公开(公告)号：EP1341643A4

公开(公告)日：2004-06-09

申请号：EP01274075

申请日：2001-11-20

Applicant: IBM ,  FREUDENBERG NONWOVENS L P

Inventor： CHEN SHYNG-TSONG ,  RODBELL KENNETH P ,  HSU OSCAR KAI CHI ,  VANGSNESS JEAN ,  GILBRIDE DAVID S ,  BILLINGS SCOTT CLAYTON ,  DAVIS KENNETH

IPC: B24B37/24 ,  B24D3/28 ,  B24D11/00 ,  B24D13/14 ,  C08J5/14 ,  H01L21/304 ,  B24B37/04

CPC classification number: B24B37/24 ,  B24D3/28 ,  B24D11/008

Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The fibers define interstices, and the precursors fill these interstices substantially completely before completion of the reaction. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers. The fibers may be separate, or in the form of a woven or non-woven web.

公开(公告)号：JP2007318132A

公开(公告)日：2007-12-06

申请号：JP2007130825

申请日：2007-05-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MURRAY CONAL EUGENE ,  LAVOIE CHRISTIAN ,  RODBELL KENNETH P

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L23/485 ,  H01L21/28518 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure of reducing the contact resistance between a silicide contact and metallization on it. SOLUTION: A structure is provided with: a semiconductor substrate 12 including at least one field effect transistor arranged on the top and including silicide contact regions 16A, 16B, and 16C arranged adjacent to at least one field effect transistor; an insulating intermediate layer 18 that is arranged on the semiconductor substrate, extended onto at least one field effect transistor, and having contact opening parts 20 exposing the silicide contact regions; and a contact material 24 containing metal germanide in the contact opening parts. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供减少硅化物接触和金属化之间的接触电阻的方法和结构。 解决方案：一种结构设置有：半导体衬底12，包括布置在顶部上的至少一个场效应晶体管，并且包括与至少一个场效应晶体管相邻布置的硅化物接触区域16A，16B和16C; 布置在半导体衬底上的绝缘中间层18延伸到至少一个场效应晶体管上，并且具有暴露硅化物接触区域的接触开口部分20; 以及在接触开口部分中含有金属锗化物的接触材料24。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004158897A

公开(公告)日：2004-06-03

申请号：JP2004063897

申请日：2004-03-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  CABRAL JR CYRIL ,  CHRISTOPHER CARL PARKS ,  RODBELL KENNETH P ,  ROGER EN-RUEN TSUAI

IPC: H01L21/3205 ,  H01L21/265 ,  H01L21/283 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To improve electromigration resistance of a copper electric conductor. SOLUTION: Impurities which improve the electromigraion resistance are added to the copper electric conductor after copper composition is deposited on inside a holding place. The impurities are C, O, C1, S and N, and a concentration level of the impurities is about 0.01ppm or about 1,000ppm. The impurities are made by electroplating copper after copper seed is deposited on inside the holding place and ion is implanted, or by electrodepositing the copper composition including the impurities and diffusing the impurities inside the copper seed layer after the copper layer is deposited, or by implanting dopant ion after the deposition of a barrier layer and then depositing the copper seed layer. Annealing is performed for diffusion. After the copper electric conductor is planarized, at least one element is ion-implanted into these surface layers. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提高铜导体的电迁移能力。 解决方案：将铜组合物沉积在保持位置之后，将改善耐电阻性的杂质加入到铜导电体中。 杂质为C，O，Cl，S和N，杂质浓度为约0.01ppm或约1,000ppm。 杂质通过将铜种子沉积在保持位置的内部并离子注入之后，或者通过电沉积包含杂质的铜组合物并在铜层沉积之后在铜籽晶层内扩散杂质，或通过植入 在沉积阻挡层之后然后沉积铜籽晶层的掺杂剂离子。 退火进行扩散。 在铜电导体平坦化之后，将至少一种元素离子注入到这些表面层中。 版权所有（C）2004，JPO