公开(公告)号：WO0209176A3

公开(公告)日：2002-05-10

申请号：PCT/EP0107782

申请日：2001-07-06

Applicant: INFINEON TECHNOLOGIES AG ,  DIEWALD WOLFGANG ,  MUEMMLER KLAUS

Inventor： DIEWALD WOLFGANG ,  MUEMMLER KLAUS

IPC: H01L21/027 ,  H01L21/02 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure (3, 4) consisting a non-metal (2) is produced in an extensive metal layer (6) and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.

Abstract translation: 根据应用半导体晶片，非金属（2）中的一个上的对准标记，现有的小规模结构的本发明的方法（3，4）在一个大面积的金属层（6），然后平坦化，在用化学机械研磨的帮助这方面的半导体晶片， 其中所述结构变量在金属层和化学机械抛光工艺协调以彼此，使得抛光工艺之后进行的大面积的金属层的小规模结构的非金属起飞。

公开(公告)号：DE102005027459A1

公开(公告)日：2006-12-28

申请号：DE102005027459

申请日：2005-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUEMMLER KLAUS ,  TEGEN STEFAN ,  BAARS PETER

IPC: H01L21/762

Abstract: The method involves selectively immersing a filling (10) with respect to an oblation layer and an intermediate layer to form a pre-determined projection of a top side of the remaining filling. The oblation layer is selectively removed based on two intermediate layers and the filling. The latter intermediate layer is immersed at ditch walls around a pre-determined height to form a gap between the filling and a semiconductor substrate. An independent claim is also included for a semiconductor structure.

公开(公告)号：DE102005055853A1

公开(公告)日：2006-06-08

申请号：DE102005055853

申请日：2005-11-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THIES ANDREAS ,  MUEMMLER KLAUS

IPC: H01L27/105 ,  G11C7/18 ,  H01L21/8239

Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

公开(公告)号：DE102004023985B4

公开(公告)日：2007-12-27

申请号：DE102004023985

申请日：2004-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEGEN STEFAN ,  MUEMMLER KLAUS

IPC: H01L21/8242 ,  G11C8/14 ,  H01L21/768 ,  H01L27/108

公开(公告)号：DE102005024952A1

公开(公告)日：2007-01-18

申请号：DE102005024952

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUEMMLER KLAUS ,  BAARS PETER ,  ARNDT CHRISTIAN ,  REGUL JOERN

IPC: H01L21/8242

Abstract: The method involves producing a conductive layer (8) on a dielectric layer (11) with opening areas above a conducting path (3) and above capacitor electrodes (7). The dielectric layer is selectively etched to the conductive layer for forming trenches that are partially dissected in a surface of the conducting path and ends in the conductive layer above the capacitor electrodes. The trenches are filled with conductive material. An independent claim is also included for a semiconductor device e.g. semiconductor memory device.

公开(公告)号：DE102004041679A1

公开(公告)日：2006-02-23

申请号：DE102004041679

申请日：2004-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NUETZEL JOACHIM ,  MUEMMLER KLAUS ,  THIES ANDREAS ,  KAMM FRANK-MICHAEL

IPC: G03F7/00 ,  G03F7/09 ,  H01L21/308 ,  H01L21/8242

Abstract: A method of lithographic production of structures in a radiation-sensitive layer, especially for semiconductor elements, comprises forming a radiation-absorbing layer (1) on or in the substrate (10) and radiating at an angle to the normal so that at least part of the structure in the sensitive layer (20) is shadowed. An independent claim is also included for a structured semiconductor substrate for the above method.

公开(公告)号：DE10037446A1

公开(公告)日：2002-02-14

申请号：DE10037446

申请日：2000-07-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIEWALD WOLFGANG ,  MUEMMLER KLAUS

IPC: H01L21/027 ,  H01L21/02 ,  H01L23/544 ,  H01L21/306 ,  G03F7/20

Abstract: The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.

公开(公告)号：DE102005024944B3

公开(公告)日：2006-12-28

申请号：DE102005024944

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEGEN STEFAN ,  MUEMMLER KLAUS

IPC: H01L21/283 ,  G11C11/24 ,  H01L21/8242

Abstract: A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings, an insulating liner and a conductive filling material prior to the patterning of bit lines.

公开(公告)号：DE102004023985A1

公开(公告)日：2005-12-08

申请号：DE102004023985

申请日：2004-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEGEN STEFAN ,  MUEMMLER KLAUS

IPC: G11C8/14 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: A process for producing an electronic storage component circuit on a semiconductor, comprises forming a crystalline silicon wall (9) on a substrate (8), and a parallel polysilicon wall (10). The walls are covered with a cover material (19) and a primary trough (20) is formed between the walls. The trough is filled with a primary filling layer, and a second trough is formed and filled with a third material. The primary insulating layer forms a gate oxide.

公开(公告)号：DE102006018235B3

公开(公告)日：2007-10-11

申请号：DE102006018235

申请日：2006-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REGUL JOERN ,  MUELLER TORSTEN ,  KAPTEYN CHRISTIAN ,  BAARS PETER ,  MUEMMLER KLAUS

IPC: H01L27/115 ,  G11C5/06 ,  H01L21/8247

Abstract: The component has a substrate at a main side, where lower bit lines (LBL1- LBL6) are formed in the substrate and are arranged parallel to each other at a distance. Word lines (WL1- WL10) are arranged over the lower bit lines parallel to each other at a distance and transverse to the lower bit lines. A gate-dielectric arranged between the word lines and cell bodies includes a memory layer as a memory medium. Lower source and/or drain regions are formed at lower lines of the bodies adjacent to the lower bit lines, and upper source and/or drain regions are formed in upper lines of the bodies. An independent claim is also included for a method for manufacturing semiconductor memory components.