公开(公告)号：US20240371637A1

公开(公告)日：2024-11-07

申请号：US18624334

申请日：2024-04-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Zhuo CHEN ,  Jinbiao LIU ,  Junfeng LI ,  Jun LUO

IPC: H01L21/02 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a channel defining layer and a source/drain layer sequentially on a substrate of a crystalline material; patterning the channel defining layer and the source/drain layer as a ridge protruding relative to the substrate; forming a channel layer on a sidewall of the ridge by deposition; and performing a crystallization process to recrystallize the channel layer.

公开(公告)号：US20180294342A1

公开(公告)日：2018-10-11

申请号：US15871690

申请日：2018-01-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinjuan XIANG ,  Xiaolei WANG ,  Hong YANG ,  Shi LIU ,  Junfeng LI ,  Wenwu WANG ,  Chao ZHAO

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L29/4966

Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

公开(公告)号：US20170186619A1

公开(公告)日：2017-06-29

申请号：US15299169

申请日：2016-10-20

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Junjie LI ,  Junfeng LI ,  Qinghua YANG ,  Jinbiao LIU ,  Xiaobin HE

IPC: H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/32136 ,  H01L21/32139

Abstract: The invention discloses a novel dry etching method, which comprises the following steps: forming a to-be-etched layer on a semiconductor substrate; forming a masking material on the to-be-etched layer; carrying out dry etching on the masking material and the to-be-etched layer; simultaneously carrying out lateral etching (parallel to the surface of the substrate) of a masking layer and longitudinal etching (vertical to the surface of the substrate) of the to-be-etched layer; and obtaining the inclination angle (the included angle between a slope surface and the surface of the substrate) of the corresponding etched slope surface by accurately controlling the speed ratio. The method can flexibly adjust the inclination angle of the etched slope surface within a large range (0-90 degrees), and especially has advantages in the field of the application with a small inclination angle (smaller than 20 degrees) of the etched slope surface in comparison with a conventional etching method.

公开(公告)号：US20250081530A1

公开(公告)日：2025-03-06

申请号：US18725967

申请日：2023-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Junjie LI ,  Enxu LIU ,  Na ZHOU ,  Jianfeng GAO ,  Junfeng LI ,  Yongliang LI ,  Jun LUO ,  Wenwu WANG

IPC: H01L29/423 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.

公开(公告)号：US20240194598A1

公开(公告)日：2024-06-13

申请号：US18532246

申请日：2023-12-07

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng GAO ,  Weibing LIU ,  Junjie LI ,  Na ZHOU ,  Tao YANG ,  Junfeng LI ,  Jun LUO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226

Abstract: A metal interconnection structure of a semiconductor device and a method for forming the same. The method includes: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive structure in the first dielectric layer; etching back part of the first conductive structure; forming an etch stop layer on the first conductive structure; forming a second dielectric layer on the etch stop layer and performing chemical mechanical polishing; and forming a second conductive structure in the second dielectric layer, where the second conductive structure is electrically connected to the first conductive structure.

公开(公告)号：US20170054001A1

公开(公告)日：2017-02-23

申请号：US14402303

申请日：2014-08-01

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinbiao LIU ,  Yao WANG ,  Guilei WANG ,  Tao YANG ,  Qing LIU ,  Junfeng LI

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L21/265 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/785

Abstract: A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.

Abstract translation: 一种制造FinFET器件的方法，包括提供衬底; 在衬底上实现源极/漏极掺杂; 蚀刻掺杂衬底以形成源区和漏区; 在源极区域和漏极区域之间形成鳍状沟道; 并在Fin通道上形成一个门。 在源极/漏极掺杂在衬底上实现之后形成鳍和栅极，使得源极/漏极掺杂作为平面器件的掺杂进行，这确保了源/漏极应对的质量并提高了其性能 的FinFET器件。

公开(公告)号：US20160211351A1

公开(公告)日：2016-07-21

申请号：US15001087

申请日：2016-01-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei WANG ,  Hushan CUI ,  Huaxiang YIN ,  Junfeng LI ,  Chao ZHAO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67 ,  C30B25/16 ,  C30B25/08 ,  C30B25/12 ,  C30B25/14 ,  H01L21/306 ,  C23C16/02

CPC classification number: H01L29/66795 ,  C30B25/08 ,  C30B25/12 ,  C30B25/14 ,  C30B25/16 ,  C30B35/00 ,  H01L21/67167

Abstract: An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.

Abstract translation: 一种用于外延生长FinFET器件的源极和漏极的装置和方法。 该装置包括：主室; 晶片加载室; 传送室，设置有用于传送晶片的机械操纵器; 用于去除晶片表面上的自然氧化物层并设置有用于定位晶片的石墨基底的蚀刻室; 至少一个外延反应室; 用于向主室，晶片装载室，传送室，蚀刻室和外延反应室供应各种气体的气体分配装置; 和真空装置。 晶片装载，转移，蚀刻和外延反应室都位于主室内。 在外延反应发生之前，在分离水和氧的条件下，将蚀刻室和外延反应室集成在晶片表面上去除天然氧化物层。

公开(公告)号：US20250063713A1

公开(公告)日：2025-02-20

申请号：US18799167

申请日：2024-08-09

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng GAO ,  Weibing LIU ,  Junjie LI ,  Na ZHOU ,  Tao Yang ,  Junfeng LI ,  Jun LUO

IPC: H10B12/00

Abstract: The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.

公开(公告)号：US20240194737A1

公开(公告)日：2024-06-13

申请号：US18529487

申请日：2023-12-05

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Junjie LI ,  Enxu LIU ,  Na ZHOU ,  Jianfeng GAO ,  Junfeng LI ,  Jun LUO ,  Wenwu WANG

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for manufacturing a semiconductor and a semiconductor. The method includes: providing a substrate, wherein an active region trench is on the substrate, and a channel stack of a gate-all-around transistor is formed in the active region trench, the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect; and filling gaps between the crystal planes with different orientations of the source crystal structure and the drain crystal structure by using an isotropic metal material, and forming a source and a drain of the gate-all-around transistor in the source trench and the drain trench, respectively.

公开(公告)号：US20210384080A1

公开(公告)日：2021-12-09

申请号：US17004173

申请日：2020-08-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guilei WANG ,  Henry H. RADAMSON ,  Zhenzhen KONG ,  Junjie LI ,  Jinbiao LIU ,  Junfeng LI ,  Huaxiang YIN

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.