VACUUM PLASMA PROCESSOR APPARATUS AND METHOD
    3.
    发明申请
    VACUUM PLASMA PROCESSOR APPARATUS AND METHOD 审中-公开
    真空等离子体处理装置和方法

    公开(公告)号:WO0203763B1

    公开(公告)日:2003-03-13

    申请号:PCT/US0120263

    申请日:2001-06-26

    CPC classification number: H01J37/321

    Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

    Abstract translation: 200mm和300mm晶片在相同或具有相同几何形状的真空等离子体处理室中进行处理。 对于不同尺寸的晶片,具有不同几何形状的基本上平面的激励线圈通过在腔室的顶部处的电介质窗口向等离子体提供电磁场,从而激发腔室中的可电离气体到等离子体。 两个线圈包括与线圈的中心点同轴的多个对称的基本圆形的匝和至少一个相对于线圈中心点不对称的匝。 两个线圈包括四圈,r.f. 激励被施加到最接近线圈中心点的转弯。 距离中心点第三远的转弯在用于200 mm晶圆的线圈中是不对称的。 线圈中心点最近的两个转弯在用于300毫米晶圆的线圈中是不对称的。

    VACUUM PLASMA PROCESSOR APPARATUS AND METHOD
    4.
    发明申请
    VACUUM PLASMA PROCESSOR APPARATUS AND METHOD 审中-公开
    真空等离子体处理装置和方法

    公开(公告)号:WO0203763A8

    公开(公告)日:2002-04-04

    申请号:PCT/US0120263

    申请日:2001-06-26

    CPC classification number: H01J37/321

    Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

    Abstract translation: 200mm和300mm晶片在相同或具有相同几何形状的真空等离子体处理室中进行处理。 对于不同尺寸的晶片,具有不同几何形状的基本上平面的激励线圈通过在腔室的顶部处的电介质窗口向等离子体提供电磁场,从而激发腔室中的可电离气体到等离子体。 两个线圈包括与线圈的中心点同轴的多个对称的基本圆形的匝和至少一个相对于线圈中心点不对称的匝。 两个线圈包括四圈,r.f. 激励被施加到最接近线圈中心点的转弯。 距离中心点第三远的转弯在用于200 mm晶圆的线圈中是不对称的。 在线圈中心点最近的两个转弯在用于300毫米晶圆的线圈中是不对称的。

    SELECTIVITY CONTROL IN A PLASMA PROCESSING SYSTEM
    5.
    发明公开
    SELECTIVITY CONTROL IN A PLASMA PROCESSING SYSTEM 审中-公开
    选择性控制在等离子处理系统

    公开(公告)号:EP1697970A4

    公开(公告)日:2008-08-06

    申请号:EP04815227

    申请日:2004-12-21

    Applicant: LAM RES CORP

    CPC classification number: H01L21/31116 H01L21/31138 H01L21/76811

    Abstract: A method in a plasma processing system for etching a feature through a given layer on a semiconductor substrate. The method includes placing the substrate in a plasma processing chamber of the plasma processing system. The method also includes flowing an etchant gas mixture into the plasma processing chamber, the etchant gas mixture being configured to etch the given layer. The method additionally includes striking a plasma from the etchant source gas. Furthermore, the method includes etching the feature at least partially through the given layer while applying a bias RF signal to the substrate, the bias RF signal having a bias RF frequency of between about 45 MHz and about 75 MHz. The bias RF signal further has a bias RF power component that is configured to cause the etch feature to be etched with an etch selectivity to a second layer of the substrate that is higher than a predefined selectivity threshold.

    TUNING VIA FACET WITH MINIMAL RIE LAG
    6.
    发明申请
    TUNING VIA FACET WITH MINIMAL RIE LAG 审中-公开
    通过最小的RIE LAG调整

    公开(公告)号:WO2009036053A3

    公开(公告)日:2009-05-07

    申请号:PCT/US2008075841

    申请日:2008-09-10

    CPC classification number: H01L21/76804 H01L21/76807 H01L22/12 H01L22/20

    Abstract: A method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over via. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained.

    Abstract translation: 提供了一种设计蚀刻配方的方法。 执行蚀刻,包括提供具有设定的卤素与碳的比例的蚀刻气体,从蚀刻气体形成等离子体,以及蚀刻通过过孔的沟槽。 测量通过面。 卤素与碳的比例根据测量的通孔面重置,其中如果测量太多的小面积,则卤素与碳的比例将增加,并且如果测量的面积太小,则卤素与碳的比率降低。 重复前面的步骤,直到获得所需的刻面数量。

    SELECTIVITY CONTROL IN A PLASMA PROCESSING SYSTEM
    7.
    发明申请
    SELECTIVITY CONTROL IN A PLASMA PROCESSING SYSTEM 审中-公开
    等离子体处理系统中的选择性控制

    公开(公告)号:WO2005062885A3

    公开(公告)日:2006-09-28

    申请号:PCT/US2004043115

    申请日:2004-12-21

    CPC classification number: H01L21/31116 H01L21/31138 H01L21/76811

    Abstract: A method in a plasma processing system for etching a feature through a given layer on a semiconductor substrate. The method includes placing the substrate in a plasma processing chamber of the plasma processing system. The method also includes flowing an etchant gas mixture into the plasma processing chamber, the etchant gas mixture being configured to etch the given layer. The method additionally includes striking a plasma from the etchant source gas. Furthermore, the method includes etching the feature at least partially through the given layer while applying a bias RF signal to the substrate. The bias RF signal has a bias RF frequency of between about 27 MHz and about 75 MHz and a bias RF power component that is configured to cause the etch feature to be etched with an etch selectivity to a second layer of the substrate that is higher than a predefined selectivity threshold or configured to cause the feature to be etched in accordance to predefined etch rate parameters and etch profile parameters at the bias RF frequency.

    Abstract translation: 一种用于通过半导体衬底上的给定层蚀刻特征的等离子体处理系统中的方法。 该方法包括将基板放置在等离子体处理系统的等离子体处理室中。 该方法还包括将蚀刻剂气体混合物流动到等离子体处理室中,蚀刻剂气体混合物被配置为蚀刻给定层。 该方法还包括从蚀刻剂源气体冲击等离子体。 此外,该方法包括至少部分地通过给定层蚀刻特征,同时向衬底施加偏置RF信号。 偏置RF信号具有在约27MHz至约75MHz之间的偏置RF频率以及被配置为使蚀刻特征被蚀刻的偏压RF功率分量,其中衬底的第二层的蚀刻选择性高于 预定义的选择性阈值或者被配置为根据预定的蚀刻速率参数和偏置RF频率下的蚀刻轮廓参数来对特征进行蚀刻。

    METHOD FOR REPAIRING LOW-K DIELECTRIC DAMAGE
    9.
    发明申请
    METHOD FOR REPAIRING LOW-K DIELECTRIC DAMAGE 审中-公开
    修复低K电介质损伤的方法

    公开(公告)号:WO2011050062A3

    公开(公告)日:2011-08-04

    申请号:PCT/US2010053377

    申请日:2010-10-20

    CPC classification number: H01L21/3105 H01L21/76814 H01L21/76826

    Abstract: A method for repairing damage to a silicon based low-k dielectric layer with organic compounds, where damage replaces a methyl attached to silicon with a hydroxyl attached to silicon is provided. A repair gas comprising CH4 gas is provided. The repair gas is formed into a plasma, while maintaining a pressure below 50 mTorr. Hydroxyl attached to silicon is replaced with methyl from the plasma formed by the repair gas.

    Abstract translation: 提供了用有机化合物修复对基于硅的低k电介质层的损伤的方法,其中损伤用连接到硅上的羟基连接到硅上的甲基替代。 提供了包含CH 4气体的修复气体。 将修复气体形成为等离子体,同时保持低于50mTorr的压力。 与由修复气体形成的等离子体中的甲基取代成硅的羟基。

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