公开(公告)号：JP2002117686A

公开(公告)日：2002-04-19

申请号：JP2001287008

申请日：2001-09-20

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To realize a memory device which can read out information having high speed and high reliability, in some parts of a memory and having high information storage density, in other parts of the memory. SOLUTION: A multi-level memory device has a memory section (multilevel array), including cells being programmable with the prescribed number of level being larger than 2 and a memory section (bilevel array), including cells being programmable with the number of level of 2. The multilevel array is used for storing high density data, in which read speed is not essential such as storing an operation code of a system, including a memory device. The bilevel array is used for storing data required to have high speed and reliability, such as BIOS of a personal computer and data stored in a cache memory, in which the read-out speed is essential such as, storing an operation code of a system, including a memory device. A circuit part, being exclusive for all the functions required for programming, writing of test instructions, and operation of a memory device is common to both arrays.

公开(公告)号：JP2000235799A

公开(公告)日：2000-08-29

申请号：JP2000034209

申请日：2000-02-10

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02

Abstract: PROBLEM TO BE SOLVED: To read out a multi-level cell quickly and reliably. SOLUTION: A multi-level memory 50 stores words formed by plural binary sub-words in plural cells 63a, each cell has a threshold value. Cells are arranged in rows and columns, grouped to plural sectors 56 divided in a block 57, selected through a global row decoder 51, a global column decoder 54, and plural local row decoder 58. These decoders supply simultaneously ramp voltage VR to a bias terminal of selected cell. Threshold value read-out comparators 72a, 72b are connected to the selected cell, when ramp voltage reaches a threshold value of the selected cell, a threshold value achievement signal is generated. Switch means 65a... are arranged between a global word line 52 and local word lines 59a..., 60a..., opening of the switch means is controlled individually by a threshold value achievement signal, thereby, a local word line is kept to respective threshold voltage of each selected cell after release.

公开(公告)号：JPH11219590A

公开(公告)日：1999-08-10

申请号：JP31506698

申请日：1998-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

IPC: G11C11/41 ,  G11C8/18

Abstract: PROBLEM TO BE SOLVED: To provide the method and circuit for adjusting the duration time of an ATD signal pulse which have respectively a functional feature and a structural feature capable of eliminating defects accompanying possible solution by conventional technology. SOLUTION: In this method and circuit for adjusting a pulse synchronizing signal ATD about the reading phase of a memory cell in a semiconductor integrated electronic memory device, a pulse signal ATD is generated in accordance with detecting variation of at least one logic state of plural address input terminals of a memory cell, and an equalizing signal SAEQ for a sense amplifier is also generated. When row voltage reaches the prescribed value being sufficient for realizing highly reliable reading by row voltage, the SAEQ pulse is interrupted (STOP). It is profitable that the interruption of the pulse is caused by the logic signal STOP activated in accordance with exceeding the prescribed voltage value during over-boosting phase of a row of an addressed memory.

公开(公告)号：JP2001028197A

公开(公告)日：2001-01-30

申请号：JP2000196290

申请日：2000-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZAMMATTIO MATTEO ,  CAMPARDO GIOVANNI

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/12

Abstract: PROBLEM TO BE SOLVED: To provide bias to a plurality of memory sectors in a memory element by bulk of a smaller region in a non-volatile memory element of especially a flash type and providing method for bias in a memory element. SOLUTION: A memory element 21 having a plurality of memory sectors 15 each sector of which includes a plurality of memory cells 1 is provided with a hierarchical sector decoding means. One group out of a plurality of groups of bias lines 28-32 is provided to each sector row, and is extended in parallel to a sector row. Each of a plurality of sector switching stages 35 is connected between a corresponding memory sector and a group corresponding to a bias line. A sector switching stage connected to memory sectors arranged in the same sector column is controlled by the same control signals S0, S1 supplied to a control line 40 extending in parallel to a sector column.

公开(公告)号：JP2000357396A

公开(公告)日：2000-12-26

申请号：JP2000139757

申请日：2000-05-12

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MANSTRETTA ALESSANDRO ,  MICHELONI RINO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory having a row redundancy function in which an access time for a memory word is drastically shortened. SOLUTION: In a non-volatile memory device having a memory cell in which rows and columns are arranged and being provided with at least one sector 100 of a matrix cell, a row decoder D and a column decoder decoding an address signal and activating rows and columns respectively, and at least one sector 110 of a redundancy cell, and being able to replace a row of a sector of a matrix cell by a row of a sector of the redundancy cell, the device is provided with a local column decoder J for a sector 100 of a matrix cell and a local column decoder L for a sector 110 of the redundancy cell. Local column decoders L for a matrix cell and for the redundancy cell are controlled by the outside signal so that rows of the sector 110 of the redundancy cell and rows of the sector 100 of a matrix cell are simultaneously activated.

公开(公告)号：JPH0883500A

公开(公告)日：1996-03-26

申请号：JP14503495

申请日：1995-06-12

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CAMERLENGHI EMILIO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  H01L27/00

Abstract: PURPOSE: To obtain a memory device endurable in a gain reduction. CONSTITUTION: Column and/or row address decode means RDEC, CDEC comprise at least one address mapping nonvolatile memory NVM. A read and write control logic part CL comprises identifying means TST designed so as to identify a cell fail in a column and/or a row of a matrix MAT of a memory device; and means WM for writing an address corresponding to a column and/or a row RID existing in the matrix MAT on the nonvolatile memory NVM during normal operations, and cell characteristics can readily and effectively be decided.

公开(公告)号：JP2001035179A

公开(公告)日：2001-02-09

申请号：JP2000187530

申请日：2000-06-19

Applicant: ST MICROELECTRONICS SRL ,  MITSUBISHI ELECTRIC CORP

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  OBA ATSUSHI ,  CARRERA MARCELLO

IPC: G11C16/06 ,  G11C8/08 ,  G11C11/56 ,  G11C16/12 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To enable biasing selectively a word line by positive or negative voltage with a simple method for a circuit. SOLUTION: This decoder is provided in a first reference line 42, a second reference line 44, a third reference line 46 and a word line WL respectively, and the decoder is provided with a bias circuit 54 receiving a row selecting signal SR at an input and transmitting a bias signal R for each word line WL at an output, an output driver circuit 60 supplying the bias signal R from each bias circuit 54 to an output 96, and a level conversion circuit 58 receiving the row selecting signal SR at an input and supplying a control signal CM to an output 84 for each driver circuit 60.

公开(公告)号：JPH11316713A

公开(公告)日：1999-11-16

申请号：JP36793098

申请日：1998-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  GIANNINI GIUSEPPE ,  GHEZZI STEFANO ,  TORRICELLI PIERO ENRICO

IPC: G06F1/00 ,  G06F12/14 ,  G06F21/00 ,  G06F21/24 ,  G07F7/10 ,  G11C8/20 ,  G11C16/22

Abstract: PROBLEM TO BE SOLVED: To use a storage area of OTP (which can be program-controlled only once) and to satisfy all necessary conditions related to safety and reliability and the facility of access with respect to the constitution of a protected storage device. SOLUTION: In a method for protecting data in the semiconductor electronic storage device constituted of a storage matrix 2, respective matrix address decoding blocks 3 and a pre-decoding block, the protected storage part 5 in the matrix 2 and private decoding parts 6 and 7 are used so that a protection code CP is stored in a protected part without the address area of the matrix. The protection code CP is written and/or read only through a command translator 8.

公开(公告)号：JPH0855486A

公开(公告)日：1996-02-27

申请号：JP6942595

申请日：1995-03-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34

Abstract: PURPOSE: To maintain the precision of a virgin cell for a long period and improve the reliability of the circuit by using the virgin cell which has characteristics shifted by a voltage shifter. CONSTITUTION: A cell and virgin cells 12 and 13 have gate-source voltages lower than a source voltage through voltage shifters 14 and 15 and their characteristics depend upon an operating load. In read mode, a logical signal R is low and a logical signal V is high, so switches 21, 26, 29, 33, and 40 are closed and a switch 42 is opened. When the source voltage is lower than 2.3V as the threshold voltage of the cells 12 and 13, the cells 11, 12, and 13 are turned off. When the source voltage exceeds it, the cells 12 and 13 turn on, but their characteristics become smaller than a logical slope because of the presence of the load. The cell 11 is off between 2.3V and the source voltage and then a current flows to neither a load transistor 18 nor a mirror transistor 23; and only the cell 12 has a high resistance value and a current is made to flow through a load transistor 30 for supply current limitation.

公开(公告)号：JPH0750398A

公开(公告)日：1995-02-21

申请号：JP4720994

申请日：1994-03-17

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

Abstract: PURPOSE: To prevent the occurrences of stress in the drain terminal of an unselected memory cell in a selected bit line by biasing a positive voltage with respect to the drain terminal of the unselected memory cell for a substrate region and by making the source terminal remain floating. CONSTITUTION: This memory array is provided with a drain region 29 arranged into rows and columns and connected to each of bit lines BL, a source region 30 connected to each source line 24, a control gate region connected to each word line WL, and a large number of memory cells 21 each having a substrate region 28 housing the drain and source regions. A drain terminal of an unselected memory cell, which is connected to a selected bit line during a reading step but not connected to the selected word line and is not connected to the source terminal of the selected memory cell, is biased with a positive voltage with respect to the substrate region 28. The source terminal is kept floating.