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    1.
    发明专利
    未知

    公开(公告)号：DE69614248D1

    公开(公告)日：2001-09-06

    申请号：DE69614248

    申请日：1996-05-31

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PISATI VALERIO ,  ALINI ROBERTO ,  COSENTINO GAETANO ,  VAI GIANFRANCO

    IPC: H03F3/45 ,  H03F3/72 ,  H03H1/00

    Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

    3.
    发明专利
    未知

    公开(公告)号：DE69614501T2

    公开(公告)日：2002-04-11

    申请号：DE69614501

    申请日：1996-03-08

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PISATI VALERIO

    IPC: H03L7/099 ,  H03B1/00

    Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

    5.
    发明专利
    未知

    公开(公告)号：DE69426776T2

    公开(公告)日：2001-06-13

    申请号：DE69426776

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PORTALURI SALVATORE

    IPC: G06G7/16 ,  G06G7/163

    Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.

    6.
    发明专利
    未知

    公开(公告)号：DE69614248T2

    公开(公告)日：2001-11-15

    申请号：DE69614248

    申请日：1996-05-31

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PISATI VALERIO ,  ALINI ROBERTO ,  COSENTINO GAETANO ,  VAI GIANFRANCO

    IPC: H03F3/45 ,  H03F3/72 ,  H03H1/00

    Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

    7.
    发明专利
    未知

    公开(公告)号：DE69614501D1

    公开(公告)日：2001-09-20

    申请号：DE69614501

    申请日：1996-03-08

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PISATI VALERIO

    IPC: H03L7/099 ,  H03B1/00

    Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

    8.
    发明专利
    未知

    公开(公告)号：IT1302276B1

    公开(公告)日：2000-09-05

    申请号：ITMI982076

    申请日：1998-09-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FILORAMO PIETRO ,  COSENTINO GAETANO ,  PALMISANO GIUSEPPE

    IPC: G05F3/26

    Abstract: A current mirror circuit is provided with recovery having high output impedance. The current mirror includes a differential stage having a pair of transistors, and a voltage feedback loop which is stabilized and closed on a first one of the transistors of the differential stage. A second one of the transistors of the differential stage is connected, by its base terminal, to the collector terminal of an output transistor and, by its collector terminal, to the supply voltage. Moreover, the circuit includes a positive feedback loop which has the second transistor of the differential stage and the output transistor. A low-impedance circuit branch is connected to the base terminal of the second transistor of the differential stage and to the collector terminal of the output transistor.

    9.
    发明专利
    未知

    公开(公告)号：DE69830173D1

    公开(公告)日：2005-06-16

    申请号：DE69830173

    申请日：1998-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FILORAMO PIETRO ,  COSENTINO GAETANO

    IPC: H03L7/189 ,  H03L7/10 ,  H03J5/02

    Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, which comprise a phase comparator (2), a filter (4), a digital-analog converter (8) and an adder (5) which are suitable to produce in output a voltage (Vc) for controlling a voltage-controlled oscillator (6) provided by means of a varactor, characterized in that it comprises the steps of: determining the dependency of the control voltage (Vc) of the voltage-controlled oscillator (6) on the frequency of a selected channel of a transmitter; generating a law describing the variation of the output current (IDAC) of said digital-analog converter (8) such that the voltage (VDAC) obtained from the output current of the digital-analog converter, added to an output voltage (Vf) of said filter (4), is such as to keep said filter voltage (Vf) constant, in order to reduce the settling time of the PLL circuit as a selected channel varies.

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