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公开(公告)号：DE69614248D1
公开(公告)日：2001-09-06
申请号：DE69614248
申请日：1996-05-31
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PISATI VALERIO , ALINI ROBERTO , COSENTINO GAETANO , VAI GIANFRANCO
Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).
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公开(公告)号：DE69614501T2
公开(公告)日：2002-04-11
申请号：DE69614501
申请日：1996-03-08
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PISATI VALERIO
Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.
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公开(公告)号：DE69624460D1
公开(公告)日：2002-11-28
申请号：DE69624460
申请日：1996-01-26
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： ALINI ROBERTO , BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , PISATI VALERIO
Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage. The amplifier has a very low or zero offset (Vos = Vout-Vin).
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公开(公告)号：DE69614248T2
公开(公告)日：2001-11-15
申请号：DE69614248
申请日：1996-05-31
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PISATI VALERIO , ALINI ROBERTO , COSENTINO GAETANO , VAI GIANFRANCO
Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).
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公开(公告)号：DE69614501D1
公开(公告)日：2001-09-20
申请号：DE69614501
申请日：1996-03-08
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PISATI VALERIO
Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.
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Patent Agency Ranking
公开(公告)号：JPH10126171A
公开(公告)日：1998-05-15
申请号：JP35901596
申请日：1996-12-27
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor： ALINI ROBERTO , BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , PISATI VALERIO
Abstract: PROBLEM TO BE SOLVED: To approximate the offset to zero by connecting directly together a drive stage of a complementary push-pull constitution and an output stage, which are cascaded with mutually reverse polarities between the input and output terminals of an amplifier. SOLUTION: A drive stage consists of an input branch part, including a 3rd transistor TR Q3 which is connected in series to a 1st constant current generator G1 between a power terminal and the ground, and a current mirror circuit which includes an output branch part consisting of TR Q4, Q5 and Q6. Then the bases and collectors of the pnp TR Q5 and the npn TR Q6 are connected to an input terminal IN and an output terminal OUT of an amplifier respectively. The emitter of the TR Q5 is connected to a power terminal via a 2nd constant current generator G2, and the emitter of the TR Q6 is grounded via the TR Q4. The output of the drive stage is fetched from the TRs Q5 and Q6 and connected to the bases of the TRs Q1 and Q2 respectively. A bipolar TR can also be converted into an FET.
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公开(公告)号：JPH0831122A
公开(公告)日：1996-02-02
申请号：JP12230495
申请日：1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: PURPOSE: To obtain a servo signal processing device which is effectively used by a parallel structure PRML reading apparatus. CONSTITUTION: This device is used in a parallel structure PRML reading apparatus comprising a variable-gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23 and a couple of individual parallel processing channels 24, 34 sandwiched between the transversal analog filter 23 and RLL-NRZ decoder 25. Two processing channels 24, 34 are respectively provided with analog-digital converters 26, 36 and subsequent viterbi detectors 27, 37 and are operated depending on alternate sampling systems. The servo signal processing device 30 is provided with a rectifier 31 and an integrator 32 connected to the analog digital converters 26, 36.
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公开(公告)号：JP2001291049A
公开(公告)日：2001-10-19
申请号：JP2001052695
申请日：2001-02-27
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , CAZZANIGA MARCO , VENCA ALESSANDRO
Abstract: PROBLEM TO BE SOLVED: To provide a low supply voltage analog multiplier for supplying an extremely low supply voltage and improving the linearity of input while keeping a sufficient speed by performing the cascade connection of plural stages. SOLUTION: A pair of differential cells 10 and 11 are provided and the respective differential cells are provided with a pair of bipolar transistors 2, 3, 6 and 7 whose emitters are connected to each other. The first transistors 2 and 6 of the respective cells 10 and 11 receive input signals IN+ and IN- at the base terminals and the collector terminals are connected to a first reference voltage Vcc through bias members 4 and 8. The second transistors 3 and 7 of the respective cells are diode constitution and the cells are mutually connected at a common node A corresponding to the base terminals of the second transistors 3 and 7 of the respective pairs.
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9.发明专利
公开(公告)号：JPH11249708A
公开(公告)日：1999-09-17
申请号：JP36474598
申请日：1998-12-22
Applicant: ST MICROELECTRONICS SRL
Inventor： PORTALURI SALVATORE , PISATI VALERIO
Abstract: PROBLEM TO BE SOLVED: To provide a feed forward(FF) circuit structure with which delay can be programmed according to a request while maintaining the suitable band width of signals. SOLUTION: This FF circuit structure provided with programmable zero is provided with first and second cells to be cascade connected. The said first and second cells are respectively provided with the first and second pairs of bipolar transistors, a first high impedance element, a second high element and a fifth transistor 8. The base terminal of the fifth transistor 8 receives a signal, which is outputted from the collector terminal of the first pair of first transistors 1, to be outputted as a positive code at the first cell but to be outputted as a negative code at the second cell in order to determine a transmission function having a pair of special points in molecules. A second transistor 2 in the said pair of first and second transistors 1 and 2 is controlled by respective third and fourth current sources 11 and 9 having different values.
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10.发明专利
公开(公告)号：JP2001285027A
公开(公告)日：2001-10-12
申请号：JP2001040561
申请日：2001-02-16
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: PROBLEM TO BE SOLVED: To obtain a feedforward type circuit structure, having programmable zero which composes a time-continual filter, a delaychain, etc. SOLUTION: A couple of amplification cells (14, 15) are connected to each other at a node A and connected between a 1st signal (Vin) input IN of a 1st cell 14 and an output terminal U of a 2nd cell 15, and each cell is equipped with a couple of transistors (10, 2; 6, 7) which have a common conduction terminal and other conduction terminals coupled with a 1st voltage reference Vcc through respective bias members. Furthermore, a node X of the 1st cell 14 is connected to the output terminal U and a transistor 8 has a control terminal connected to a node X of the 1st cell 14, a 1st conduction terminal connected to an output terminal U, and a 2nd conduction terminal coupled with a 2nd voltage reference GND through a capacitor Cc. The transistor 8 is equipped with a circuit leg 13.
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