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公开(公告)号：DE69614248D1
公开(公告)日：2001-09-06
申请号：DE69614248
申请日：1996-05-31
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PISATI VALERIO , ALINI ROBERTO , COSENTINO GAETANO , VAI GIANFRANCO
Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).
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公开(公告)号：DE69614248T2
公开(公告)日：2001-11-15
申请号：DE69614248
申请日：1996-05-31
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PISATI VALERIO , ALINI ROBERTO , COSENTINO GAETANO , VAI GIANFRANCO
Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).
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公开(公告)号：DE69624460D1
公开(公告)日：2002-11-28
申请号：DE69624460
申请日：1996-01-26
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： ALINI ROBERTO , BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , PISATI VALERIO
Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage. The amplifier has a very low or zero offset (Vos = Vout-Vin).
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公开(公告)号：JPH10126171A
公开(公告)日：1998-05-15
申请号：JP35901596
申请日：1996-12-27
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor： ALINI ROBERTO , BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , PISATI VALERIO
Abstract: PROBLEM TO BE SOLVED: To approximate the offset to zero by connecting directly together a drive stage of a complementary push-pull constitution and an output stage, which are cascaded with mutually reverse polarities between the input and output terminals of an amplifier. SOLUTION: A drive stage consists of an input branch part, including a 3rd transistor TR Q3 which is connected in series to a 1st constant current generator G1 between a power terminal and the ground, and a current mirror circuit which includes an output branch part consisting of TR Q4, Q5 and Q6. Then the bases and collectors of the pnp TR Q5 and the npn TR Q6 are connected to an input terminal IN and an output terminal OUT of an amplifier respectively. The emitter of the TR Q5 is connected to a power terminal via a 2nd constant current generator G2, and the emitter of the TR Q6 is grounded via the TR Q4. The output of the drive stage is fetched from the TRs Q5 and Q6 and connected to the bases of the TRs Q1 and Q2 respectively. A bipolar TR can also be converted into an FET.
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公开(公告)号：JPH0773140A
公开(公告)日：1995-03-17
申请号：JP5280994
申请日：1994-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor： ALINI ROBERTO , MOLONEY DAVID , GORNATI SILVANO , PORTALURI SALVATORE
Abstract: PURPOSE: To reduce the integration area and to accelerate the processing concerning a structure provided with a serial type interface for connection to a data transmission line, by connecting a part of a register to the bundled line and transmitting both a register address and data. CONSTITUTION: A decoded address latch 5 stores the output state of an address decoder 4 until the other address is transmitted through a multiplex bus 2. Only when this address is the address of a designated data register 1, according to the output of this latch 5, data transmitted after this address are written in this register. A write line 9 transmits a data write signal through a logic gate 7 of AND type. A data read circuit means 3 reads data out of this register 1 so as to repeat data from the multiplex bus 2. Only when the transmitted address is as prescribed, a read command starts reading from this register 1.
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Patent Agency Ranking
公开(公告)号：JPH07176138A
公开(公告)日：1995-07-14
申请号：JP25471694
申请日：1994-09-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , BETTI GIORGIO , ALINI ROBERTO
Abstract: PURPOSE: To prevent the generation of errors by the transmission delay of signals by storing bits finally processed in a second combinational logic network (RC1) in a shift register, predicting the time when (n) bits are process in a first RC1 and synthesizing the signals in a second RC2. CONSTITUTION: The first RC1 processes the Q output tap (6:0) value of an FF for forming the shift register SR prior to the processing by the second RC2 of the corresponding bit for the complete two cycles of a synchronous block signal VCO. In order to secure the utilization of the entire cycle of the clock signal VCO which is a corresponding decoding value ND1 in the input D of the output register (FF) of a decoding NRZ output stream, a frequency which is partial compared to the base synchronous clock signal VCO in front of the rising front of a first clock signal and matched with the bit number ratio of input and output streams is provided. The bit finally processed in the RC2 is tentatively stored in the shift registers Q1-Q7, the time when the (n) bits are processed in the RC1 is predicted and the signals are synthesized in the RC2.
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公开(公告)号：JPH0879006A
公开(公告)日：1996-03-22
申请号：JP20722395
申请日：1995-08-14
Applicant: ST MICROELECTRONICS SRL
Inventor： BRIANTI FRANCESCO , ALINI ROBERTO , PISATI VALERIO , GADDUCCI PAOLO
IPC: H03H11/04
Abstract: PROBLEM TO BE SOLVED: To constitute a fourth cell which operates with a low supply power, does not require any floating capacitance, and has a low capacitance load at its input terminal. SOLUTION: A high-pass filter constituted of a current generating circuit 29 which is particularly used for high frequencies, has at least each one of input terminal IN and output terminal OUT, between which a transfer function (Fdt) is formed, incorporates serially arranged transconductance stages 2-5, is connected between a pair of stages 2 and 3 of a fourth cell 18 and a reference voltage (GND), and generates variable currents iK1 and iK2 . The circuit 29 makes the introduction of a programmable zero to the transfer function (Fdt) of the filter 20 possible.
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公开(公告)号：JPH0865064A
公开(公告)日：1996-03-08
申请号：JP19561095
申请日：1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ALINI ROBERTO , CASTELLO RINALDO , VAI GIANFRANCO
Abstract: PROBLEM TO BE SOLVED: To control the gain of integrator with built-in transconductor by changing the output resistance of active load. SOLUTION: This device comprises a transconductance stage 3 having two input terminals I1 and I2 at least and two output terminals O1 and O2 at least and provided with an active load 4 connected to the output terminals O1 and O2 on the transconductance stage 3 and control circuit 5 for active load 4 connected between the output terminals O1 and O2 and the active load 4.
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公开(公告)号：JPH06196948A
公开(公告)日：1994-07-15
申请号：JP21157793
申请日：1993-08-26
Applicant: ST MICROELECTRONICS SRL
Inventor： CASTELLO RINALDO , ALINI ROBERTO , REZZI FRANCESCO , PISATI VALERIO
Abstract: PURPOSE: To provide a mutual conductor stage for dealing with a high frequency signal. CONSTITUTION: A mutual conductor stage 1 has signal input parts A and B and signal output parts U1 and U2 and is provided with a pair of FET (M1 and M2 ) sharing gates G1 and G2 and sources S1 and S2 , and its output is composed of a pair of bipolar transistors Q1 and Q2 connected to these FET M1 and M2 .
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公开(公告)号：JPH07320404A
公开(公告)日：1995-12-08
申请号：JP11572495
申请日：1995-05-15
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , ALINI ROBERTO
Abstract: PURPOSE: To obtain a partial response signal (PRML) device by maximum likelihood sequence detection displaying no conventional fault. CONSTITUTION: This device has a variable gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23, and two separate parallel sampling channels 24, 34 inserted between the transversal analog filter 23 and a finite run length-non-return-to-zero type decoder 25. These sampling channels 24, 34 have analog-digital converters 26, 36 operated in accordance with sampling sequences, in which these each sampling channel is continued mutually and alternated mutually, and Viterbi detectors 27, 37.
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