公开(公告)号：JPH11205122A

公开(公告)日：1999-07-30

申请号：JP31113198

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To combine a voltage shift driving circuit having the functional and constitutional features usable by both high voltage and low voltage and capable of reducing the area of a circuit further with a final output stage for supplying power to a load. SOLUTION: In this high voltage final output stage for electric load driving which is constituted of a pair of the transistors of complementary combination connected between a first reference power source (Vdd) and a second reference power source (Vss) and in which the pair of the transistors are constituted by connecting in series at least one PMOS pull-up transistor (MP1) to an NMOS pull-down transistor (MN), an additional PMOS transistor (MP2) is connected in parallel to the PMOS pull-up transistor (MP1) and its body terminal is made to be in common with the PMOS pull-up transistor (MP1).

公开(公告)号：JPH11234118A

公开(公告)日：1999-08-27

申请号：JP31113098

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To provide an electronic level shift circuit for driving a high voltage output stage. SOLUTION: An output stage 2 is provided with a complementary pair of transistors I36 and I32 including at least one PMOS pull-up transistor I32 connected between a first reference voltage source Vdd and a second reference voltage source Vss and serially connected to an NMOS pull-down transistor I36. An additional transistor I34 is parallelly connected to the pull-up transistor I32 and a driving circuit 1 is provided with a first output terminal A connected to the control terminal of the pull-up transistor I32 and a second output terminal B connected to the control terminal of the additional transistor I34.

公开(公告)号：JPH04270513A

公开(公告)日：1992-09-25

申请号：JP18241991

申请日：1991-07-23

Applicant: ST MICROELECTRONICS SRL

Inventor： VIO FABIO ,  DIAZZI CLAUDIO ,  PIDUTTI ALBINO ,  MARTIGNONI FABRIZIO

IPC: H03K17/567 ,  H03K3/356 ,  H03K17/687 ,  H03K19/0185

Abstract: PURPOSE: To provide a circuit which drives the floating circuit, in response to a binary-coded decimal signal and is small in power consumption in a stationary state. CONSTITUTION: This circuit has two DMOS transistors(TR) 10 and 12 which are actuated with a digital signal IN and driven in opposite phase by respective gates. The two DMOS TRs 10 and 12 are biased by current mirrors 16 and 18, which reflect a reference current IBIAS and auxiliary circuits 34 to 44 which impress other current pulses during switching. Two DMOS TRs 20 and 22 operate as loads with respect to the two DMOS TRs 10 and 12. Since two Zener diodes 24 and 26 can be used to limit the voltages between the gates and sources of the MOS TRs 20 and 22. A drive output part of the floating circuit may be a drain of one of the DMOS TRs.

公开(公告)号：DE69524858D1

公开(公告)日：2002-02-07

申请号：DE69524858

申请日：1995-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： RAVANELLI ENRICO M A ,  MARTIGNONI FABRIZIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06

公开(公告)号：DE69727918D1

公开(公告)日：2004-04-08

申请号：DE69727918

申请日：1997-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SCIAN ENRICO ,  MARTIGNONI FABRIZIO ,  DEPETRO RICCARDO

IPC: G11C11/413 ,  G05F3/20 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/08 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K17/10

Abstract: The invention relates to a method, and related circuit, for preventing the triggering of a parasitic transistor in an output stage (2) of an electronic circuit, said stage (2) comprising a transistor pair (M1,M2) with at least one transistor (M2) of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor (3) having a terminal connected to said body terminal, characterized in that it comprises the steps of: providing a capacitor (C1) connected between the body and source terminals of the PMOS transistor; using a control circuit (5) to suppress the body effect of the pull-up PMOS transistor.

公开(公告)号：IT1243692B

公开(公告)日：1994-06-21

申请号：IT2108790

申请日：1990-07-27

Applicant: ST MICROELECTRONICS SRL

Inventor： VIO FABIO ,  DIAZZI CLAUDIO ,  PIDUTTI ALBINO ,  MARTIGNONI FABRIZIO

IPC: H03K17/567 ,  H03K3/356 ,  H03K17/687 ,  H03K19/0185 ,  H03K

Abstract: A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (IBIAS), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective load for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and the source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.

公开(公告)号：DE69524858T2

公开(公告)日：2002-07-18

申请号：DE69524858

申请日：1995-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： RAVANELLI ENRICO M A ,  MARTIGNONI FABRIZIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06

公开(公告)号：DE69131532D1

公开(公告)日：1999-09-23

申请号：DE69131532

申请日：1991-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： VIO FABIO ,  DIAZZI CLAUDIO ,  PIDUTTI ALBINO ,  MARTIGNONI FABRIZIO

IPC: H03K17/567 ,  H03K3/356 ,  H03K17/687 ,  H03K19/0185 ,  H03K17/06

Abstract: A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (IBIAS), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective load for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and the source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.

公开(公告)号：DE69533309D1

公开(公告)日：2004-09-02

申请号：DE69533309

申请日：1995-05-17

Applicant: ST MICROELECTRONICS SRL

Inventor： DIAZZI CLAUDIO ,  MARTIGNONI FABRIZIO ,  TARANTOLA MARIO

IPC: G01R19/165 ,  H01L21/8234 ,  H01L27/088 ,  H02J1/00 ,  H03K17/06 ,  H03K17/0814 ,  H03K17/687 ,  H03K17/081

公开(公告)号：DE69131532T2

公开(公告)日：2000-04-06

申请号：DE69131532

申请日：1991-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： VIO FABIO ,  DIAZZI CLAUDIO ,  PIDUTTI ALBINO ,  MARTIGNONI FABRIZIO

IPC: H03K17/567 ,  H03K3/356 ,  H03K17/687 ,  H03K19/0185 ,  H03K17/06

Abstract: A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (IBIAS), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective load for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and the source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.