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公开(公告)号：JP2001229691A
公开(公告)日：2001-08-24
申请号：JP2000374346
申请日：2000-12-08
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , MICHELONI RINO , PIERIN ANDREA , YERO EMILIO
Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory device having row redundancy being freely constituted in which correcting capability of architecture can be reconstituted for each chip. SOLUTION: This device comprises a row decoding circuit 12 and a column decoding circuit 13, a circuit reading out stored data in a memory cell and changing it, a memory matrix 14 which can store a fault row address, and a control circuit. The device also comprises a circuit comparing a fault row address stored in the memory matrix 14 with a selected row address in order to recognize a selected row address ADr and perform relieving selection of a fault row and selection of a corresponding redundant cell row at the time of recognizing validness, and configuration register comprising a matrix of a non-volatile memory cell and a control circuit.
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公开(公告)号：JP2002319293A
公开(公告)日：2002-10-31
申请号：JP2002107937
申请日：2002-04-10
Applicant: ST MICROELECTRONICS SRL
Inventor： GREGORI STEFANO , MICHELONI RINO , PIERIN ANDREA , KHOURI OSAMA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To realize a method for speedily and highly precisely programming a memory cell. SOLUTION: In the method for programming a non-volatile memory cell 1, at least first and second programming pulse trains F1, F2 having pulse width increasing in stages are applied continuously to a control terminal 2 of the memory cell 1, but amplitude increment between a pulse in the first programming train F1 and the next one is made larger than the amplitude increment between a pulse in the second programming train F2 and the next one. Advantageously, third programming pulse trains F0, F3, having pulse width which increases in stages, are applied to the control terminal 2 of the memory cell 1 before the first programming pulse train F1, but amplitude increment between a pulse and the next one is made smaller than the amplitude increment in the first programming train F1, and is substantially equal to the amplitude increment in the second programming train F2 or larger than the amplitude increment in the first programming train F1.
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公开(公告)号：JP2000067592A
公开(公告)日：2000-03-03
申请号：JP14849699
申请日：1999-05-27
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To provide a selector switch, integrated monolithically for a device containing an electrically programmable memory cell, which has a simple circuit and operation capability adapted to various use. SOLUTION: Selector switches are integrated monolithically in a circuit of CMOS technology for a memory cell device being electrically programmable and having at least first and second input terminals connecting with first (HV) and second (LV) voltage generators respectively and an output terminal (OUT). First (P1) and second (P2) field effect selection transistors are connected between the first input terminal and the output terminal and the second input terminal and the output terminal respectively through a first and second terminal.
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公开(公告)号：JP2003153525A
公开(公告)日：2003-05-23
申请号：JP2002302131
申请日：2002-10-16
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , PIERIN ANDREA , SOLTESZ DARIO , TORRELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption both in an operation mode state and in a stand-by mode state. SOLUTION: A charge pump circuit, connected between a reference voltage line and an output terminal, has at least two circuit stages having respective charge pump circuit elements. The circuit stages are connected between the reference voltage line and the output terminal, respectively. Further, the charge pump circuit has a control circuit, connected between the output terminal and the control terminals of the respective two circuit stages. The charge pump circuit selects a proper combination of the circuit stages, according to the current absorbed by a load connected to the output terminal.
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公开(公告)号：JPH11260087A
公开(公告)日：1999-09-24
申请号：JP37435798
申请日：1998-12-28
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To alleviate a total load by providing a second and a third field effect transistors having the conductivity types same as or opposite to the first field effect transistor, providing a body connecting terminal to the first terminal thereof and then connecting the first terminal of the first transistor to the bias of the memory device. SOLUTION: A row driver includes a source terminal connected to a first drive voltage VBODY, a gate terminal connected to a bias voltage generator G1, a drain terminal connected to an input terminal IN of row driver and a PMOS transistor M1 having the body terminal connected to the source terminal. The row driver also includes a phase inverter I coupled between the input terminal IN and output terminal OUT. M1 is 'on' or 'off' depending on the voltage impressed to the node G1 in regard to the selected word line and M2 bomes 'on' while M3 becomes 'off' in the triode area.
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Patent Agency Ranking
公开(公告)号：DE60134477D1
公开(公告)日：2008-07-31
申请号：DE60134477
申请日：2001-11-09
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , SOLTESZ DARIO , PIERIN ANDREA , TORELLI GUIDO
Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages consisting of an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.
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公开(公告)号：DE69901259T2
公开(公告)日：2002-12-05
申请号：DE69901259
申请日：1999-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).
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公开(公告)号：ITMI20001585D0
公开(公告)日：2000-07-13
申请号：ITMI20001585
申请日：2000-07-13
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , TORELLI GUIDO , MICHELONI RINO , PIERIN ANDREA , GREGORI STEFANO , SANGALLI MIRIAM
IPC: G11C16/08
Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.
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公开(公告)号：DE69901259D1
公开(公告)日：2002-05-16
申请号：DE69901259
申请日：1999-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).
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公开(公告)号：ITMI20001585A1
公开(公告)日：2002-01-14
申请号：ITMI20001585
申请日：2000-07-13
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , TORELLI GUIDO , MICHELONI RINO , PIERIN ANDREA , GREGORI STEFANO , SANGALLI MIRIAM
IPC: G11C16/08
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