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1.发明授权Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 失效方法和电路，用于产生一个地址转换信号ATD以调节访问非易失性存储器
公开(公告)号：EP0915477B1
公开(公告)日：2004-03-17
申请号：EP97830576.1
申请日：1997-11-05
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino , Maccarrone, Marco , Zammattio, Matteo
IPC: G11C8/00
CPC classification number: G11C8/18
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公开(公告)号：EP0668591B1
公开(公告)日：1999-10-20
申请号：EP94830074.4
申请日：1994-02-18
Applicant: STMicroelectronics S.r.l.
Inventor： Pascucci, Luigi , Padoan, Silvia , Golla, Carla Maria , Maccarrone, Marco , Olivo, Marco
CPC classification number: G11C7/02 , G11C7/1006 , G11C7/22 , G11C16/32
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公开(公告)号：EP0805556B1
公开(公告)日：2005-03-23
申请号：EP96830247.1
申请日：1996-04-30
Applicant: STMicroelectronics S.r.l.
Inventor： Maccarrone, Marco , Ghezzi, Stefano , Branchetti, Maurizio
IPC: H03K17/22
CPC classification number: H03K17/223
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公开(公告)号：EP0805456B1
公开(公告)日：2004-02-11
申请号：EP96830242.2
申请日：1996-04-30
Applicant: STMicroelectronics S.r.l.
Inventor： Maccarrone, Marco , Mulatti, Jacopo , Golla, Carla Maria
CPC classification number: G11C16/30
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5.发明授权Read method and circuit for nonvolatile memory cells with an equalizing structure 失效阅读非易失性存储单元与均衡器的方法和电路
公开(公告)号：EP0814483B1
公开(公告)日：2003-08-27
申请号：EP96830347.9
申请日：1996-06-18
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino , Maccarrone, Marco
IPC: G11C16/06
CPC classification number: G11C16/28
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Patent Agency Ranking
公开(公告)号：EP0665485B1
公开(公告)日：1998-10-07
申请号：EP94830022.3
申请日：1994-01-21
Applicant: STMicroelectronics S.r.l.
Inventor： Maccarrone, Marco , Olivo, Marco , Golla, Carla Maria
IPC: G05F3/26
CPC classification number: G05F3/262
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7.发明授权
公开(公告)号：EP0661636B1
公开(公告)日：1998-09-23
申请号：EP93830528.1
申请日：1993-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： Pascucci, Luigi , Padoan, Silvia , Maccarrone, Marco
IPC: G06F11/20
CPC classification number: G11C29/70
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公开(公告)号：EP0666571B1
公开(公告)日：2000-05-31
申请号：EP94830030.6
申请日：1994-01-28
Applicant: STMicroelectronics S.r.l.
Inventor： Pascucci, Luigi , Maccarrone, Marco , Padoan, Silvia
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9.发明授权Circuit architecture and corresponding method for testing a programmable logic matrix 失效电路结构和方法用于测试可编程逻辑矩阵
公开(公告)号：EP0655683B1
公开(公告)日：1999-09-01
申请号：EP93830478.9
申请日：1993-11-30
Applicant: STMicroelectronics S.r.l.
Inventor： Maccarrone, Marco , Olivo, Marco
IPC: G06F11/267 , G11C29/00
CPC classification number: G01R31/318516 , G11C29/48
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10.发明公开Low consumption TTL-CMOS input buffer stage 失效TTL-CMOS Eingangspufferstufe mit geringem Leistungsverbrauch
公开(公告)号：EP0928068A1
公开(公告)日：1999-07-07
申请号：EP97830743.7
申请日：1997-12-31
Applicant: STMicroelectronics S.r.l.
Inventor： Mulatti, Jacopo , Maccarrone, Marco , Martines, Ignazio , Micheloni, Rino
IPC: H03K19/00 , H03K19/0185
CPC classification number: H03K19/0016
Abstract: The invention relates to a low-consumption TTL-CMOS input buffer stage (10) of the type which comprises a chain of inverters (11,12,13,14) cascade connected between an input (APAD) receiving electric signals at a TTL logic level and an output (ADD) reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference (Vcc) and a second or ground reference (GND). Advantageously, the first inverter (11) in the chain includes a means (15,MP2,MN2) of selecting the delivery path to the stage (10) according to an activate signal (LOWPOWER) for a low-consumption operation mode.
In essence, the first inverter (11) of the buffer (10) has two signal paths, one for normal operation, and the other for low consumption operation.Abstract translation: 本发明涉及一种低功耗TTL-CMOS输入缓冲器级（10），其包括串联连接在以TTL逻辑电路接收电信号的输入端（APAD）之间的反相器链（11,12,13,14） 电平和输出（ADD）以CMOS逻辑电平再现电信号，并且在第一或电源电压参考（Vcc）和第二或接地参考（GND）之间供电。 有利地，链中的第一反相器（11）包括根据用于低功耗操作模式的激活信号（LOWPOWER）选择到级（10）的传送路径的装置（15，MP2，MN2）。 实质上，缓冲器（10）的第一反相器（11）具有两个信号路径，一个用于正常操作，另一个用于低功耗操作。
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