公开(公告)号：KR101354457B1

公开(公告)日：2014-01-28

申请号：KR1020120083405

申请日：2012-07-30

Applicant: 한국과학기술원

Inventor： 류승탁 ,  오길근

IPC: H03K5/13 ,  H03M1/12

CPC classification number: H03M1/64 ,  H03K5/131 ,  H03M1/0624 ,  H03M1/124 ,  H03M1/14 ,  H03M2201/2372 ,  H03M2201/75

Abstract: A clock signal generator for pipelined analog-to-digital converter having no sample and hold amplifier (SHA) is disclosed. The clock signal generator used in an SHA-less pipelined analog-to-digital convertor (ADC) comprises: a phase detector for receiving an external clock signal inputted from the outside and a delay clock signal generated by delaying the external clock signal to detect and output phase difference; a charge pump circuit unit for receiving output outputted from the phase detector to generate control voltage corresponding to the phase difference; a delay circuit for receiving the control voltage generated by the charge pump circuit unit and delaying the external clock signal inputted as a delay value corresponding to the control voltage to generate the delay clock signal and feeding back the delay clock signal to the phase detector; and a non-overlapping clock generator for receiving the delay clock signal and the external clock signal to generate a required clock signal. According to an embodiment of the present invention, a sampling time can be directly synchronized with the external clock signal to reduce errors. [Reference numerals] (401) Phase detector; (402) Charge pump; (403) Delay cell; (404) Non-overlapping clock generator; (AA) External clock signal; (BB) Reference current; (CC) Output of the phase detector; (DD) Control voltage; (EE) Delayed clock

Abstract translation: 公开了一种没有采样和保持放大器（SHA）的流水线模数转换器的时钟信号发生器。 在无SHA流水线模数转换器（ADC）中使用的时钟信号发生器包括：相位检测器，用于接收从外部输入的外部时钟信号和延迟时钟信号，延迟外部时钟信号以检测和 输出相位差; 电荷泵电路单元，用于接收从相位检测器输出的输出，以产生对应于相位差的控制电压; 延迟电路，用于接收由电荷泵电路单元产生的控制电压，并延迟作为对应于控制电压的延迟值输入的外部时钟信号，以产生延迟时钟信号，并将延迟时钟信号反馈给相位检测器; 以及不重叠的时钟发生器，用于接收延迟时钟信号和外部时钟信号以产生所需的时钟信号。 根据本发明的实施例，采样时间可以与外部时钟信号直接同步，以减少误差。 （附图标记）（401）相位检测器; （402）电荷泵; （403）延迟单元; （404）非重叠时钟发生器; （AA）外部时钟信号; （BB）参考电流; （CC）相位检测器的输出; （DD）控制电压; （EE）延迟时钟

公开(公告)号：KR1020090061507A

公开(公告)日：2009-06-16

申请号：KR1020070128534

申请日：2007-12-11

Applicant: 한양대학교 산학협력단

Inventor： 유창식 ,  조준기 ,  박재우 ,  신성철

IPC: H03M1/12

CPC classification number: H03M1/502 ,  H03M1/002 ,  H03M1/1205 ,  H03M1/362 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/2372 ,  H03M2201/322 ,  H03M2201/61

Abstract: An analog to digital converter and an analog to digital converting method are provided to reduce power consumption and a chip size in comparison with the analog to digital converter comprised of a plurality of comparators comprised of pre-amplifiers. A reference voltage generator(10) generates a plurality of different reference voltages. A delay unit(20) changes a size of an analog input signal and the size and difference of a plurality of reference voltages into the delay time difference of an inputted clock. A phase detector(30) detects the delay time difference of the clock and generates the detection signal. A code generator(100) receives the detection signal and converts the detection signal into an N bit digital signal which increases as the analog input signal increases. The delay unit includes a first delay cell and a second delay cell. The first delay cell receives the clock and delays the clock as much as the first delay time according to the analog input signal. The second delay cell receives the clock and delays the clock as much as the second delay time according to the one reference voltage among the plurality of reference voltages.

Abstract translation: 与由前置放大器组成的多个比较器组成的模数转换器相比，提供了模数转换器和模数转换方法来降低功耗和芯片尺寸。 参考电压发生器（10）产生多个不同的参考电压。 延迟单元（20）将模拟输入信号的大小和多个参考电压的大小和差异改变为输入时钟的延迟时间差。 相位检测器（30）检测时钟的延迟时间差并产生检测信号。 代码生成器（100）接收检测信号，并将检测信号转换成随着模拟输入信号增加而增加的N位数字信号。 延迟单元包括第一延迟单元和第二延迟单元。 第一延迟单元接收时钟，并根据模拟输入信号将时钟延迟到第一延迟时间。 第二延迟单元接收时钟，并根据多个参考电压中的一个参考电压将时钟延迟多达第二延迟时间。

公开(公告)号：KR1020150041819A

公开(公告)日：2015-04-20

申请号：KR1020130120241

申请日：2013-10-10

Applicant: 울산과학기술원 산학협력단

Inventor： 김재준 ,  박경환

IPC: H03M1/34

CPC classification number: H03M1/0607 ,  H03M1/34 ,  H03M1/64 ,  H03M2201/2372 ,  H03M2201/615

Abstract: 본발명의아날로그지연고정루프를이용한 ADC 비교기는, 입력신호의레벨과 n비트의아날로그출력신호의레벨을비교하여하이또는로우레벨의비교신호를출력하는비교기와, 출력되는상기비교신호를입력으로하여그 위상차를검출하는위상검출기와, 상기위상검출기로부터제공되는위상차검출신호에대한전류소오스의제어를통해출력전압을업 또는다운시킴으로써, 상기비교기에서의오프셋을보정하기위한제어신호를발생하여상기비교기로공급하는전하펌프를포함할수 있다.

Abstract translation: 使用本发明的模拟延迟锁定环的ADC比较器包括：比较器，用于通过将输入信号的电平与n位的模拟信号的输出电平的电平进行比较来输出高电平或低电平的比较信号; 相位检测器，用于通过输入输出比较信号来检测相位差; 通过对从相位检测器提供的相位差检测信号的电流源的控制，上下输出电压; 以及电荷泵，用于通过产生用于向比较器提供控制信号以校正比较器的偏移。

公开(公告)号：KR101012741B1

公开(公告)日：2011-02-09

申请号：KR1020090121902

申请日：2009-12-09

Applicant: 경상대학교산학협력단

Inventor： 정세교

IPC: H03M1/64

CPC classification number: H03M1/1023 ,  H03M1/645 ,  H03M2201/2372 ,  H03M2201/615 ,  H03M2201/63

Abstract: PURPOSE: A resolver digital converter and a method compensating phase thereof are provided to compensate a position measurement error due to phase delay by compensating the phase the output signal from a resolver. CONSTITUTION: A resolver(110) detects an output signal which is changed according to the angular displacement of a rotor. A sinusoidal wave generator(120) generates sinusoidal wave to apply created sinusoidal wave to the resolver. A current amplifier(130) amplifies the current of the created sinusoidal wave and applies it to the resolver. A phase compensator(140) generates a phase compensation signal to make the phase of the created sinusoidal wave same as the phase of the signal outputted from the resolver. A resolver digital conversion circuit(150) converts the phase information of the resolver into a digital signal by using the creased phase compensation signal and the outputted signal from the resolver.

Abstract translation: 目的：提供一个分解数字转换器及其补偿相位的方法，通过补偿来自旋转变压器的输出信号的相位来补偿相位延迟引起的位置测量误差。 构成：解算器（110）检测根据转子的角位移而改变的输出信号。 正弦波发生器（120）产生正弦波以将产生的正弦波施加到旋转变压器。 电流放大器（130）放大产生的正弦波的电流并将其施加到旋转变压器。 相位补偿器（140）产生相位补偿信号，以使所生成的正弦波的相位与从旋转变压器输出的信号的相位相同。 解算器数字转换电路（150）通过使用折线相位补偿信号和来自旋转变压器的输出信号将解算器的相位信息转换为数字信号。

公开(公告)号：KR1020000044544A

公开(公告)日：2000-07-15

申请号：KR1019980061043

申请日：1998-12-30

Applicant: 에스케이하이닉스 주식회사

Inventor： 정진면

IPC: H03M7/30

CPC classification number: H03M1/48 ,  H03M1/50 ,  H03M3/00 ,  H03M2201/2372

Abstract: PURPOSE: A signal phase difference quantizing circuit is provided to be capable of quantizing a phase difference between two signals by a simple circuit configuration. CONSTITUTION: A signal phase difference quantizing circuit comprises a NOR gate(NOR2), a buffer chain(20) and a plurality of D-flip flops(21-25). The NOR gate(NOR2) receives a first input signal(S0) and a second input signal(S1) having a predetermined phase difference with the first input signal(S0), and outputs a phase difference signal(S-diff) between the first and second input signals(S0,S1). The buffer chain(20) consists of a plurality of buffers(B1-Bn) each corresponding to the D-flip flops(21-25) and having an unit delay time. Each of the D-flip flops(21-25) has a clock terminal(CLK) connected to receives an inverted version of the phase difference signal(S-diff) and a data input terminal(D) connected to receive an output signal of a corresponding buffer. Each of the D-flip flops(21-25) stores an output signal of a corresponding buffer when the phase difference signal(S-diff) transitions from high to low, and is reset by a signal(END) indicating that a processing of a quantized signal is completed.

Abstract translation: 目的：提供信号相位差量化电路，以便通过简单的电路配置量化两个信号之间的相位差。 构成：信号相位差量化电路包括NOR门（NOR2），缓冲链（20）和多个D-触发器（21-25）。 NOR门（NOR2）接收与第一输入信号（S0）具有预定相位差的第一输入信号（S0）和第二输入信号（S1），并输出第一输入信号 和第二输入信号（S0，S1）。 缓冲链（20）由多个缓冲器（B1-Bn）组成，每个缓冲器对应于D触发器（21-25）并具有单位延迟时间。 每个D触发器（21-25）具有连接的时钟端子（CLK），以接收相位差信号（S-diff）的反相版本和连接的数据输入端子（D），以接收 一个相应的缓冲区。 当相位差信号（S-diff）从高转变为低时，每个D触发器（21-25）存储相应缓冲器的输出信号，并且通过指示处理 量化信号完成。