公开(公告)号：KR1020090062271A

公开(公告)日：2009-06-17

申请号：KR1020070129413

申请日：2007-12-12

Applicant: 한국전자통신연구원

Inventor： 박봉혁 ,  이승식 ,  최상성 ,  김석기 ,  김윤정

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/1205 ,  H03M2201/11 ,  H03M2201/61 ,  H03M2201/718 ,  H03M2201/8132

Abstract: A latch and an analog to digital converter are provided to perform a high speed operation by sensing a current and a voltage in the latch at the same time. A latch includes first to tenth transistor and an inverter(141,142). A first step of the first transistor is connected to a first power source to supply the first power and responds to a reference clock. The second transistor is connected a first node forming a first input terminal. The first step of the second transistor is connected to the second step of the first transistor. A control terminal of the third transistor is connected to a second node forming a second input terminal. The first step of the third transistor is connected to the second step of the first transistor. The control terminal of the fourth transistor is connected to the third node forming the first output terminal and the first step of the fourth transistor is connected to the second node. The second step of the fourth transistor is connected to the fourth node forming the second output terminal. The control terminal of the fifth transistor is connected to the fourth node. The first step of the fifth transistor is connected to the first node and the second step of the fifth transistor is connected to the third node.

Abstract translation: 提供锁存器和模数转换器以通过同时检测锁存器中的电流和电压来执行高速操作。 闩锁包括第一至第十晶体管和反相器（141,142）。 第一晶体管的第一步骤连接到第一电源以提供第一功率并响应参考时钟。 第二晶体管连接形成第一输入端的第一节点。 第二晶体管的第一级连接到第一晶体管的第二级。 第三晶体管的控制端子连接到形成第二输入端子的第二节点。 第三晶体管的第一级连接到第一晶体管的第二级。 第四晶体管的控制端子连接到形成第一输出端子的第三节点，第四晶体管的第一步骤连接到第二节点。 第四晶体管的第二步连接到形成第二输出端的第四节点。 第五晶体管的控制端子连接到第四节点。 第五晶体管的第一级连接到第一节点，第五晶体管的第二级连接到第三节点。

公开(公告)号：KR1020080086752A

公开(公告)日：2008-09-26

申请号：KR1020070028844

申请日：2007-03-23

Applicant: 인하대학교 산학협력단

Inventor： 윤광섭 ,  김판수

IPC: H03M1/12

CPC classification number: H03M1/0634 ,  H03M2201/22 ,  H03M2201/6107 ,  H03M2201/6327 ,  H03M2201/6354 ,  H03M2201/8132

Abstract: A resistor averaging circuit is provided to adjust an averaging resistor value according to an input frequency by obtaining an optimal resistance according to the input frequency and then changing the optimal resistance. A resistor averaging circuit receives a pre-amplifier load resistance(R0) and an output voltage of a pre-amplifier stage. An averaging resistor(R1) is series-connected to the resistor averaging circuit, which outputs an averaged voltage through a BOTTOM terminal. An interpolation block(2) is arranged to be adjacent to the averaging resistor. MOS(Metal Oxide Semiconductor) transistors are series-connected in the interpolation block. The averaging resistor outputs 2^(n-1) optimal resistor values according to an input frequency. Two averaging resistors are series-connected to form one averaging resistor.

Abstract translation: 提供电阻平均电路，通过根据输入频率获得最佳电阻，然后改变最佳电阻，根据输入频率调整平均电阻值。 电阻平均电路接收前置放大器负载电阻（R0）和前置放大器级的输出电压。 平均电阻（R1）串联连接到电阻平均电路，其通过BOTTOM端子输出平均电压。 插值块（2）被布置成与平均电阻器相邻。 MOS（金属氧化物半导体）晶体管串联在插值块中。 平均电阻根据输入频率输出2 ^（n-1）个最优电阻值。 两个平均电阻串联连接形成一个平均电阻。

公开(公告)号：KR1020050101649A

公开(公告)日：2005-10-25

申请号：KR1020040026724

申请日：2004-04-19

Applicant: 페어차일드코리아반도체 주식회사

Inventor： 정진화 ,  정문상 ,  연상흠

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/194 ,  H03M2201/8132 ,  H03M2201/932

Abstract: 본 발명은 디지털 서보 시그널을 위한 D/A 변환 인터페이스에 관한 것이다. 본 발명에 따르면 복잡한 D/A 컨버터나 외부에 커패시터와 저항을 필요로 하는 OP 앰프 없이 D/A 변환 인터페이스를 구성하며, 3개의 정전류원과 동일한 타입의 2개의 스위치를 사용한다. 이와 같이 하면 스위칭 속도 차이로 인한 신호 왜곡이 발생하지 않기 때문에 모터를 정밀하게 제어할 수 있다.

公开(公告)号：KR20100093214A

公开(公告)日：2010-08-25

申请号：KR20090012304

申请日：2009-02-16

Applicant: PUSAN NAT UNIV IND COOP FOUND

Inventor： NAM IL KU ,  LEE HYUNG SU ,  SEO SHIN HYOUK ,  CHOI JAE YI

IPC: H03M1/12

CPC classification number: H03M1/068 ,  H03M1/66 ,  H03M2201/8132 ,  H03M2201/931

Abstract: PURPOSE: A differential digital-to-analog converter using the complementary characteristic is provided to reduce unnecessary power consumption and whole system size by omitting a secondary circuit forming a differential phase clock. CONSTITUTION: A current supplying unit(100) includes one current source. The current supplying unit supplies a current corresponding to the output of a digital-to-analog converter by forming a p-type metal-oxide-semiconductor transistor with a current mirror. A current distributing unit(200) distributes a current from the current supplying unit into a plurality of distributed currents. A switching unit(300) controls the flow of the distributed currents. An impedance buffering unit(400) minimizes a current variation according to the switching operation of a switching unit. A voltage outputting unit(500) generates an outputting voltage by adding distributed currents.

Abstract translation: 目的：提供使用互补特性的差分数模转换器，通过省略形成差分相位时钟的次级电路来减少不必要的功耗和整个系统尺寸。 构成：电流供应单元（100）包括一个电流源。 电流供给单元通过形成具有电流镜的p型金属氧化物半导体晶体管来提供与数 - 模转换器的输出相对应的电流。 电流分配单元（200）将来自电流供应单元的电流分配到多个分布电流中。 开关单元（300）控制分布电流的流动。 阻抗缓冲单元（400）根据切换单元的切换操作使电流变化最小化。 电压输出单元（500）通过增加分布电流产生输出电压。

公开(公告)号：KR1020000074467A

公开(公告)日：2000-12-15

申请号：KR1019990018439

申请日：1999-05-21

Applicant: 에스케이하이닉스 주식회사

Inventor： 김병두

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/194 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/8132 ,  H03M2201/932

Abstract: PURPOSE: A digital-analog converter used for an LCD driver is provided to minimize time delay and line resistance of data signal lines to improve the efficiency of a system. CONSTITUTION: A digital-analog converter used for an LCD driver includes a controller(100) for receiving data signals(D0,D1) to generate control signals(C1-C4), a controller(110) for receiving data signals(D2,D3) to generate control signals(C5-C8), an inverter(120) for inverting the eight control signals, and a selector(130) for receiving high power supply voltages(VH0-VH15) having different voltage levels to selectively output them according to the fifth to eighth control signals. The digital-analog converter also includes a selector(140) for power supply voltages(VL0-VL15) having different voltage levels to selectively output them according to the first to fourth control signals, and a selector(150) for accepting the output signals of the two selectors to selectively output them as output signals(POUT,NOUT) according to the output signal of the inverter.

Abstract translation: 目的：提供用于LCD驱动器的数模转换器，以最小化数据信号线的延时和线路电阻，从而提高系统的效率。 构成：用于LCD驱动器的数模转换器包括用于接收数据信号（D0，D1）以产生控制信号（C1-C4）的控制器（100），用于接收数据信号（D2，D3）的控制器 ）产生控制信号（C5-C8），用于反转八个控制信号的反相器（120），以及用于接收具有不同电压电平的高电源电压（VH0-VH15）的选择器（130），以根据 第五到第八控制信号。 数模转换器还包括用于具有不同电压电平的电源电压（VL0-VL15）的选择器（140），以根据第一至第四控制信号选择性地输出它们;以及选择器（150），用于接收 两个选择器根据变频器的输出信号选择性地输出它们作为输出信号（POUT，NOUT）。