公开(公告)号：WO2009129273A3

公开(公告)日：2010-01-21

申请号：PCT/US2009040586

申请日：2009-04-14

Applicant: ALTERA CORP ,  NGUYEN ANDY ,  YU LING

Inventor： NGUYEN ANDY ,  YU LING

IPC: G01R19/165

CPC classification number: G01R19/16552

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

Abstract translation: 电路可以包括比较器，电阻分压器，控制电路和多路复用器。 比较器将电路的内部电源电压与选定的参考电压进行比较。 电阻分压器产生参考电压。 控制电路接收比较器的输出信号并产生选择信号。 复用器响应于选择信号，将参考电压中的一个从电阻分压器传送到比较器作为选择的参考电压。

公开(公告)号：WO2007005472A3

公开(公告)日：2009-04-30

申请号：PCT/US2006025197

申请日：2006-06-26

Applicant: ALTERA CORP ,  O HUGH-SUNGKI ,  SHIH CHIH-CHING ,  HUANG CHENG-HSIUNG ,  LIU YOW-JUANG BILL

Inventor： O HUGH-SUNGKI ,  SHIH CHIH-CHING ,  HUANG CHENG-HSIUNG ,  LIU YOW-JUANG BILL

IPC: H02H9/00 ,  H02H1/00 ,  H02H3/22

CPC classification number: H01L27/0285

Abstract: An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.

Abstract translation: ESD器件发明包括形成在衬底中的第一和第二晶体管，每个具有源极，漏极和栅极，第一事务的源极和漏极连接在地和I / O引脚或输入之间， 第一晶体管连接到地，并且第二晶体管的源极和漏极连接在第一晶体管的衬底和I / O引脚或输入之间; 在地和I / O引脚或输入之间串联连接的第一和第二电容器; 以及至少第三晶体管，其连接在第一和第二电容器之间的接地和节点之间，第二晶体管的栅极也连接到该节点。

公开(公告)号：WO2008058141A2

公开(公告)日：2008-05-15

申请号：PCT/US2007083809

申请日：2007-11-06

Applicant: ALTERA CORP ,  CHU MICHAEL H M ,  HUANG JOSEPH ,  SUNG CHIAKANG ,  CHONG YAN ,  BELLIS ANDREW ,  CLARKE PHILIP ,  ROGE MANOJ B

Inventor： CHU MICHAEL H M ,  HUANG JOSEPH ,  SUNG CHIAKANG ,  CHONG YAN ,  BELLIS ANDREW ,  CLARKE PHILIP ,  ROGE MANOJ B

IPC: G06F5/16

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract translation: 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

公开(公告)号：WO2005122356A3

公开(公告)日：2007-04-19

申请号：PCT/US2005016101

申请日：2005-05-06

Applicant: ALTERA CORP ,  HUANG CHENG-HSIUNG ,  LIN GUU ,  LEE SHIH-LIN S ,  SHIH CHIH-CHING ,  RAHIM IRFAN ,  TRAN STEPHANIE T

Inventor： HUANG CHENG-HSIUNG ,  LIN GUU ,  LEE SHIH-LIN S ,  SHIH CHIH-CHING ,  RAHIM IRFAN ,  TRAN STEPHANIE T

IPC: H02H9/00 ,  H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0251

Abstract: Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses (56). Electrostatic discharge (ESD) protection circuitry (40) is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device (44) that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit (42) that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

Abstract translation: 提供具有诸如可编程多晶硅保险丝（56）的敏感电路的集成电路。 提供静电放电（ESD）保护电路（40），其防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件（44），其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路（42），当电流跨越敏感电路施加最大电压时，该余量电路有助于防止电流流过敏感电路。

公开(公告)号：WO2007019222A2

公开(公告)日：2007-02-15

申请号：PCT/US2006030248

申请日：2006-08-02

Applicant: ALTERA CORP ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY YURYEVICH ,  MAANGAT SIMARDEEP ,  WONG WILSON ,  PATEL RAKESH

Inventor： TRAN THUNGOC M ,  SHUMARAYEV SERGEY YURYEVICH ,  MAANGAT SIMARDEEP ,  WONG WILSON ,  PATEL RAKESH

IPC: H04L25/03

CPC classification number: H04L1/243 ,  H04L25/03878

Abstract: Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

Abstract translation: 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

公开(公告)号：WO2005116879A3

公开(公告)日：2006-04-27

申请号：PCT/US2005017266

申请日：2005-05-18

Applicant: ALTERA CORP ,  RAHIM IRFAN ,  MCELHENY PETER ,  LIU YOW-JUANG W ,  PEDERSEN BRUCE

Inventor： RAHIM IRFAN ,  MCELHENY PETER ,  LIU YOW-JUANG W ,  PEDERSEN BRUCE

IPC: G06F17/50 ,  H03K19/00 ,  H03K19/003 ,  H03K19/173

CPC classification number: H03K19/1731 ,  G06F17/5054 ,  H03K19/00369 ,  H03K2217/0018

Abstract: A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract translation: 可编程逻辑器件（PLD）包括用于调整或设置一个或多个晶体管的体偏置的机构。 PLD包括体偏置发生器。 体偏置发生器被配置为设置可编程逻辑器件内的一个或多个晶体管的体偏置。 更具体地，体偏置发生器设置晶体管的体偏置，以便折衷晶体管的性能和功耗。

公开(公告)号：WO0213004A2

公开(公告)日：2002-02-14

申请号：PCT/US0141624

申请日：2001-08-07

Applicant: ALTERA CORP

Inventor： METZGEN PAUL

IPC: G06F17/50 ,  G06F9/00

CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F17/5054

Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.

Abstract translation: 提供了一种基于纯软件结构的可编程逻辑生成硬件结构的软件到硬件编译器。 更具体地，可以使用高级程序语言来创建仅使用被编译成硬件结构的软件结构的程序。 可以在编译的后期进行优化，以重新加电，允许最大数据流。 硬件可以对并行执行可编程逻辑块做出运行时决定。 决定可以至少部分地基于控制流程。

公开(公告)号：WO0052825A9

公开(公告)日：2001-11-29

申请号：PCT/US0005488

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

公开(公告)号：WO0052826A2

公开(公告)日：2000-09-08

申请号：PCT/US0005628

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Abstract translation: 可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

公开(公告)号：DE112017004291T5

公开(公告)日：2019-05-23

申请号：DE112017004291

申请日：2017-08-29

Applicant: ALTERA CORP

Inventor： LANGHAMMER MARTIN

IPC: H03K19/177 ,  G06F7/42 ,  G06F7/44

Abstract: Es sind integrierte Schaltungen mit spezialisierten Verarbeitungsblöcken bereitgestellt. Ein spezialisierter Verarbeitungsblock kann eine reale Additionsstufe und eine reale Multiplikationsstufe enthalten. Die Multiplikationsstufe kann gleichzeitig ihren Ausgang in die Additionsstufe und direkt in einen benachbarten spezialisierten Verarbeitungsblock einspeisen. Die Additionsstufe kann auch Summen- und Differenzausgänge parallel erzeugen. Eine Gruppe von vier solchen spezialisierten Verarbeitungsblöcken kann in einer Kette verbunden sein, um einen Radix-2 schnellen Fourier-Transformation-Butterfly zu implementieren. Mehrere Radix-2-Butterflies können gestapelt sein, um Butterflys einer Radix noch höherer Potenz zu bilden. Nach Wunsch kann der spezialisierte Verarbeitungsblock auch zu Implementieren einer komplexen Multiplikationsoperation verwendet werden. Drei oder vier spezialisierte Verarbeitungsblöcke können aneinander gekettet sein und gemeinsam mit einem oder mehreren Addierern außerhalb der spezialisierten Verarbeitungsblöcke können reale und imaginäre Teile eines komplexen Produkts generiert werden.