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公开(公告)号：KR1020030062489A
公开(公告)日：2003-07-28
申请号：KR1020020002695
申请日：2002-01-17
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/0634 , H01L29/7835
Abstract: PURPOSE: An extended drain metal oxide semiconductor(EDMOS) device with the structure of lattice type drift region is provided to simultaneously obtain a high breakdown voltage and low on-resistance by making an np junction composed of a high density n lattice and a low density p lattice. CONSTITUTION: A well region(204) is formed in a predetermined region on a silicon substrate(201). A lattice-type drift region in which the first lattice and the second lattice are repeatedly arranged in every direction while contacting each other is formed in a predetermined region of the well region. A field oxide layer is formed in a predetermined portion of the well region or in predetermined portions of the well region and the drift region. A drain region(213) is formed in a predetermined region inside the drift region. A diffusion region is formed under the drain region. A source region(212) and a source contact region(214) are formed in a predetermined region of the well region. A gate electrode is formed in a predetermined region on the well region by interposing a gate insulation layer. A source electrode(216) is connected to the source region and the source contact region. A drain electrode(217) is connected to the drain region.
Abstract translation: 目的：提供具有晶格型漂移区结构的延伸漏极金属氧化物半导体（EDMOS）器件，通过使np结构成高密度n格和低密度，同时获得高击穿电压和低导通电阻 p格。 构成：在硅衬底（201）上的预定区域中形成阱区（204）。 在阱区域的预定区域中形成格子型漂移区域，其中第一晶格和第二晶格在彼此接触的情况下沿每个方向重复布置。 在阱区域的预定部分或阱区域和漂移区域的预定部分中形成场氧化物层。 漏极区域（213）形成在漂移区域内的预定区域中。 在漏极区域下方形成扩散区域。 源区域（212）和源极接触区域（214）形成在阱区域的预定区域中。 通过设置栅极绝缘层，在阱区的预定区域中形成栅电极。 源极（216）连接到源区和源极接触区。 漏电极（217）连接到漏区。
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公开(公告)号：KR1020030042655A
公开(公告)日：2003-06-02
申请号：KR1020010073393
申请日：2001-11-23
Applicant: 한국전자통신연구원
IPC: G11C11/22
CPC classification number: G11C11/22
Abstract: PURPOSE: A ferroelectric memory cell array and a method for storing data by using the same are provided to form a memory cell array by using the ferroelectric memory cell array formed with a single transistor. CONSTITUTION: A ferroelectric memory cell array is formed with a plurality of memory cells(FM1-FMn,FMm-FMn+m), a plurality of word lines(WL1-WLn), a plurality of bit lines(BL1-BLm), a common source line(CSL), and a plurality of well lines(WELL1-WELLn,WELLm-WELLn+m). The memory cells are formed by stacking a ferroelectric layer, a gate, a source, and a drain on a substrate including a well. The word lines are connected with gates of the memory cells. The bit lines are connected with drains of the memory cells. The common source line is commonly connected with sources of the memory cells. The well lines are connected with wells of the memory cells. The well lines are separated electrically to each other.
Abstract translation: 目的：通过使用由单个晶体管形成的铁电存储单元阵列，提供铁电存储单元阵列和使用该存储单元阵列存储数据的方法以形成存储单元阵列。 构成：铁电存储单元阵列形成有多个存储单元（FM1-FMn，FMm-FMn + m），多个字线（WL1-WLn），多个位线（BL1-BLm）， 公共源线（CSL）和多条井线（WELL1-WELLn，WELLm-WELLn + m）。 存储单元通过在包括阱的衬底上层叠铁电体层，栅极，源极和漏极而形成。 字线与存储器单元的栅极连接。 位线与存储器单元的漏极连接。 公共源线通常与存储器单元的源相连。 井线与存储单元的孔连接。 井管线彼此电气分离。
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公开(公告)号：KR1020030042654A
公开(公告)日：2003-06-02
申请号：KR1020010073392
申请日：2001-11-23
Applicant: 한국전자통신연구원
IPC: H01L27/06
Abstract: PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.
Abstract translation: 目的：提供一种用于制造双极CMOS-DMOS（BCD）器件的方法，以通过使用CMOS器件工艺来制造电压容差为20-30伏和60-90伏特的不同厚度的栅极氧化物层的BCD器件 的亚微米级。 构成：在20-30伏等级的横向双扩散MOS（LDMOS）器件的漏极区域下方仅形成漂移区域，而在60-90伏特级别的漏极区域形成漂移区域，使得阱区域为 形成以提高耐压性和导通电阻特性。 使nLDMOS器件的栅极氧化层变薄，同时使pLDMOS器件的栅极氧化物层变厚，从而增加栅极施加电压以改善驱动能力。 使用沟槽时，通过隔离装置来减少装置占用面积。 形成DMOS器件的漂移区域，以通过使用用于形成双极器件的基极的掩模来简化工艺。
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公开(公告)号：KR1020020042228A
公开(公告)日：2002-06-05
申请号：KR1020000072033
申请日：2000-11-30
Applicant: 한국전자통신연구원
IPC: H01L21/31
CPC classification number: H01L21/0228 , C23C16/409 , C23C16/45542 , C23C16/45544 , C23C16/50 , H01L21/02194 , H01L21/02197 , H01L21/02274 , H01L21/31691 , Y10S438/905
Abstract: PURPOSE: A formation method of a Sr-Ta-O thin film is provided to improve an electrical characteristic by forming a Sr-Ta-O thin film having a high dielectric constant and a low current leakage through an atomic vaporization using plasma. CONSTITUTION: A thermal treatment is performed at the temperature of 155 - 165 deg.C, after locating a substrate to a reactive chamber(119). Then, a source having a strontium tantalum ethoxide is injected to the reactive chamber(119) by a carrier gas. An evaporated source in the carrier gas is carried to the outer of the reactive chamber(119) by an Ar gas. A plasma is formed by injecting an oxygen into the reactive chamber(119). Then, the oxygen plasma is carried to the outer of the reactive chamber(119) using the Ar gas.
Abstract translation: 目的：提供Sr-Ta-O薄膜的形成方法，以通过使用等离子体通过原子蒸发形成具有高介电常数和低电流泄漏的Sr-Ta-O薄膜来改善电特性。 构成：在将基板定位到反应室（119）之后，在155-165℃的温度下进行热处理。 然后，通过载气将具有钽酸锶钽的源注入反应室（119）。 载气中的蒸发源通过Ar气输送到反应室（119）的外部。 通过将氧注射到反应室（119）中形成等离子体。 然后，使用Ar气体将氧等离子体运送到反应室（119）的外部。
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公开(公告)号：KR102221618B1
公开(公告)日：2021-03-02
申请号：KR1020170001562
申请日：2017-01-04
Applicant: 한국전자통신연구원
Abstract: 본발명은배터리모듈및 전자디바이스에관한것이다. 본발명의실시예에따른배터리모듈은제1 전지, 제2 전지, 보정소자부, 및배터리컨트롤러를포함한다. 제1 전지는제1 내부저항을포함하고제1 전류를제공한다. 제2 전지는제1 전지와병렬로연결되고제2 내부저항을포함하고제2 전류를제공한다. 보정소자부는제1 전지또는제2 전지와연결된다. 보정소자부는가변저항을포함하거나전류원을포함한다. 배터리컨트롤러는제1 내부저항및 제2 내부저항의저항값차이에근거하여제1 전류와제2 전류가동일하도록보정소자부를제어한다. 본발명의배터리모듈및 전자디바이스는제1 전지및 제2 전지의성능악화를방지한다.
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Patent Agency Ranking
公开(公告)号：KR102147138B1
公开(公告)日：2020-08-25
申请号：KR1020140006792
申请日：2014-01-20
Applicant: 한국전자통신연구원 , 단국대학교 산학협력단
IPC: H01L27/02 , H01L21/8238 , H01L27/092
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公开(公告)号：KR101905586B1
公开(公告)日：2018-10-10
申请号：KR1020120151064
申请日：2012-12-21
Applicant: 한국전자통신연구원
IPC: G05F1/67
CPC classification number: H02J3/385 , H02M3/1588 , Y02B70/1466 , Y02E10/58
Abstract: 본발명의따른최대전력추출장치는전지, 복수의저항중 선택된저항에따라상기전지로부터출력되는제 1 전력의크기를조절하는, 그리고상기선택된저항에따라상기제 1 전력의크기가조절되는동작전압및 기준전압간의크기차이에따른비교신호를발생하는전압제어부, 상기전지와부하사이에연결되고, 제 1 및제 2 스위칭제어신호에응답하여상기비교신호의크기차이에따른상기동작전압의크기를조절하는스위칭부, 상기제 1 및제 2 스위칭제어신호를발생하여상기비교신호에따른상기동작전압및 상기기준전압간의크기를소정오차범위내로줄이는스위칭제어부, 상기비교신호가상기소정오차범위내로줄어들었을경우, 상기제 1 또는제 2 스위칭제어신호가발생한수를소정시간동안카운트한제 1 동작횟수를측정하는최대전력제어부를포함하되, 상기최대전력제어부는상기제 1 동작횟수와내부적으로저장된상기동작전압에따른상기부하에서의최대전력의크기를카운터한제 2 동작횟수를비교하며, 비교결과에따라상기복수의저항에대한선택을변경하는선택신호를발생하여상기제 1 전력의크기를조절한다.
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公开(公告)号：KR101877552B1
公开(公告)日：2018-07-12
申请号：KR1020110104117
申请日：2011-10-12
Applicant: 한국전자통신연구원
CPC classification number: H02M3/156 , H02M3/1563 , H02M2001/0006 , H02M2001/0035 , Y02B70/16
Abstract: 본발명은 DC-DC 컨버터에관한것으로서, 부하를구동시키기위한출력전압을생성하는스위치부; 기준전압을생성하는기준전압생성기와상기기준전압생성기의전력이차단되는경우상기기준전압을유지하는기준전압커패시터를포함하고, 상기출력전압을상기기준전압에맞추기위한신호를발생하는출력전압모니터링부; 상기출력전압모니터링부의신호를이용하여 PWM(Pulse Width Modulation) 모드또는 PFM(Pulse Frequency Modulation) 모드로동작하여상기스위치부를제어하는스위치제어부; 및상기부하의크기에따라상기스위치제어부의동작모드를 PWM 모드또는 PFM 모드로설정하고, PFM 모드동작시상기기준전압생성기의전력을차단하는모드결정및 전력차단부를포함한다.
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公开(公告)号：KR101736282B1
公开(公告)日：2017-05-16
申请号：KR1020110122088
申请日：2011-11-22
Applicant: 한국전자통신연구원
IPC: H01L29/78 , H01L21/336 , H01L21/28
Abstract: 반도체소자가제공된다. 본발명에따른반도체소자는반도체기판내에배치되는필라부, 상기반도체기판내에상기필라부와이격되는필드플레이트전극, 상기반도체기판내에상기필드플레이트전극상에배치되는게이트패턴, 상기필드플레이트전극은상기게이트패턴의하단과연결되는것, 상기반도체기판과상기필드플레이트전극사이에배치되는필드플레이트유전막및 상기반도체기판과상기게이트패턴의측벽사이에배치되고, 상기필드플레이트유전막보다얇은두께를갖는게이트유전패턴을포함할수 있다.
Abstract translation: 提供了一种半导体器件。 根据本发明，柱部，栅极图案，以及设置在所述半导体衬底中的场板电极的半导体装置，所述半导体衬底，所述柱部和该间隔的电极场板，在上半导体衬底提供的场板电极是 doeneungeot连接到栅极图案的下端，设置在所述半导体基板和所述场之间，所述场板电介质层和所述半导体衬底的侧壁和栅极图案被设置在电极板之间，具有厚度比所述场板电介质层更薄的栅极介电图案 在可以包含。
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