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Patent Agency Ranking
公开(公告)号：KR1019920010969B1
公开(公告)日：1992-12-26
申请号：KR1019900021855
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit optimally shares one cache memory to improve the efficiency of the cache memory when a snooper and a CPU simultaneously use the memory. The circuit includes an approach controller of processor (11) for interfacing the data needed to approach a CPU cache (4) or a CPU (1), an approach controller of snooper (12), a memory controller of cache data (13) for controlling the data state of a cache memory (6) according to the control signals from the two approach controllers (11,12), and a cache controller (3) composed of the 1st cue (Fc;14) and the 2nd cue (Fs;15).
Abstract translation: 当窥探者和CPU同时使用存储器时，电路最佳地共享一个高速缓冲存储器以提高高速缓冲存储器的效率。 该电路包括处理器（11）的接近控制器，用于将接近CPU高速缓存（4）或CPU（1）所需的数据，窥探者（12）的接近控制器，高速缓存数据（13）的存储器控制器 根据来自两个进场控制器（11,12）的控制信号，控制高速缓冲存储器（6）的数据状态，以及由第一提示（Fc; 14）和第二提示（Fs）组成的高速缓存控制器（3） ; 15）。
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公开(公告)号：KR1019920010968B1
公开(公告)日：1992-12-26
申请号：KR1019900021854
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit controls address path in a copyback and writeback mode effectively. The circuit includes a comparator (11) for generating retry signal by comparing input and output address signals with each other, a CPU cache address path former (12) for generating cache state memory (6b) address and cache tag memory (6a) address according to address signal transmitted from a CPU, a snoop cache address path former (13) for generating snoop state memory (6d) address and snoop tag memory (6c) address, a data cache address path former (14) for transmitting address signals to a data memory, and a system address bus generator (15) for transmitting address signals to a system bus controller (2) according to address signals transmitted from the cache address path former (12) and the snoop cache address former (13).
Abstract translation: 电路有效地控制了回写和回写模式下的地址路径。 该电路包括用于通过比较输入和输出地址信号而产生重试信号的比较器（11），用于产生高速缓存状态存储器（6b）地址和高速缓存标签存储器（6a）地址的CPU高速缓存地址路径形成器（12） 寻址从CPU发送的信号，用于产生窥探状态存储器（6d）地址和窥探标签存储器（6c）地址）的窥探缓存地址路径形成器（13），用于将地址信号发送到 数据存储器和系统地址总线发生器（15），用于根据从高速缓存地址路径形成器（12）和窥探缓存地址生成器（13）发送的地址信号，将地址信号发送到系统总线控制器（2）。
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公开(公告)号：KR1019920010967B1
公开(公告)日：1992-12-26
申请号：KR1019900021847
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The control circuit for requesting the use of the system bus from an external bus arbitrator with controlling the cache memory using a copy back mode according to the processor operation comprises a cache change data generator (13) for generating control signals according to the contents of a cache tag memory and a cache state memory to change the state of the cache state memory, a processor interface unit (11) for receiving the control signal from the generator (13) to halt or retry a CPU, a cache memory change signal generator (14) for transmitting a write signal to the cache state memory and cache tag memory, and a system bus request unit (12), thereby synchronizing the signals of the control circuits with the main clock to minimize the skew generation at the output stage.
Abstract translation: 根据处理器操作，通过使用复制模式控制高速缓冲存储器的外部总线仲裁器请求使用系统总线的控制电路包括：高速缓存改变数据生成器（13），用于根据处理器操作的内容生成控制信号 高速缓存标签存储器和高速缓存状态存储器以改变高速缓存状态存储器的状态;处理器接口单元（11），用于从发生器（13）接收控制信号以停止或重试CPU;高速缓存存储器改变信号发生器（ 14），用于将写入信号发送到高速缓存状态存储器和高速缓存标签存储器，以及系统总线请求单元（12），从而使控制电路的信号与主时钟同步，以使输出级的偏斜产生最小化。
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公开(公告)号：KR1019920009441B1
公开(公告)日：1992-10-16
申请号：KR1019900021861
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/10
Abstract: The state of block units of stored data and tag data is stored on a cache memory and is compared to address data transmitted through a bus within clock period having a certain delay time using the snoop controller directory so that operation speed is increased. The directory includes a state memory for storing state data of block units of stored data, an address generator for generating the state memory address signal, data and address signal for a tag memory according to address signals transmitted through bus, a tag memory for comparing address with data signal generated by the address generator and tag data to generate tag match signal, and a write enable signal generator for generating write enable signal to be transmitted to the state memory.
Abstract translation: 存储数据和标签数据的块单元的状态存储在高速缓存存储器中，并且通过使用窥探控制器目录的具有一定延迟时间的时钟周期内通过总线发送的地址数据进行比较，从而增加操作速度。 该目录包括用于存储存储数据的块单元的状态数据的状态存储器，用于产生状态存储器地址信号的地址生成器，根据通过总线发送的地址信号的标签存储器的数据和地址信号，用于比较地址的标签存储器 由地址发生器产生的数据信号和标签数据产生标签匹配信号;以及写使能信号发生器，用于产生要发送到状态存储器的写允许信号。
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