公开(公告)号：DE69023677T2

公开(公告)日：1996-06-20

申请号：DE69023677

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

公开(公告)号：DE69021594T2

公开(公告)日：1996-05-02

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：DE69018100T2

公开(公告)日：1995-10-05

申请号：DE69018100

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system is described which can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

公开(公告)号：DE69021594D1

公开(公告)日：1995-09-21

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：DE69018100D1

公开(公告)日：1995-05-04

申请号：DE69018100

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system is described which can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

公开(公告)号：CA2734039C

公开(公告)日：2017-07-11

申请号：CA2734039

申请日：2010-04-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  SEMINARO EDWARD JOSEPH ,  COVI KEVIN ROBERT ,  AHLADAS STEVEN JOHN ,  FAHR GERALD ,  BARUS DANIEL

IPC: G06F1/26 ,  H02J1/00

Abstract: A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.

公开(公告)号：CA2508041C

公开(公告)日：2011-06-07

申请号：CA2508041

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：CA2508551C

公开(公告)日：2008-12-16

申请号：CA2508551

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  GUTHRIE GUY LYNN ,  CARGNONI ROBERT ALAN

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/02

Abstract: A method and system are disclosed for saving soft state information, which i s non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memor y associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan - chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

公开(公告)号：DE69930983T2

公开(公告)日：2006-11-23

申请号：DE69930983

申请日：1999-02-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN

IPC: G06F12/08

Abstract: A modified MESI cache coherency protocol is implemented within a level two (L2) cache accessible to a processor having bifurcated level one (L1) data and instruction caches. The modified MESI protocol includes two substates of the shared state, which denote the same coherency information as the shared state plus additional information regarding the contents/coherency of the subject cache entry. One substate, SIC0, indicates that the cache entry is assumed to contain instructions since the contents were retrieved from system memory as a result of an instruction fetch operation. The second substate, SIC1, indicates the same information plus that a snooped flush operation hit the subject cache entry while its coherency was in the first shared substate. Deallocation of a cache entry in the first substate of the shared coherency state within lower level (e.g., L3) caches does not result in the contents of the same cache entry in an L2 cache being invalidated. Once the first substate is entered, the coherency state does not transition to the invalid state unless an operation designed to invalidate instructions is received. Operations from a local processor which contravene the presumption that the contents comprise instructions may cause the coherency state to transition to an ordinary shared state. Since the contents of a cache entry in the two coherency substates are presumed to be instructions, not data, instructions within an L2 cache are not discarded as a result of snooped flushes, but are retained for possible reloads by a local processor.

公开(公告)号：AU2003302510A1

公开(公告)日：2004-06-23

申请号：AU2003302510

申请日：2003-11-14

Applicant: IBM

Inventor： CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN ,  ARIMILLI RAVI KUMAR

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.