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    91.
    发明专利
    未知

    公开(公告)号：DE10219782C1

    公开(公告)日：2003-11-13

    申请号：DE10219782

    申请日：2002-05-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

    IPC: G11C29/12 ,  G11C29/40 ,  G11C29/00

    Abstract: The testing of a RAM memory circuit containing a multiplicity of memory cells can in each case be selected in groups of n>=1 memory cells by using an applied address information item in order to write in or read out groups of in each case n data. According to the invention, in a test write cycle, a plurality i=j*m of the memory cell groups are selected, where j and m are in each case integers >=2, and the same datum is written into all the memory cells of in each case m selected memory cell groups. In a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read in a sequence such that the read-out data groups from in each case m memory cell groups at which the same datum was written in are provided simultaneously or in direct succession as a read data block comprising m*n data. Each time a read data block is provided, a compressed test result is determined and provided; the result indicates if all m*n data of the read data block provided correspond to the datum written therein.

    Integrated circuit has screen for protecting strip conductor section from electromagnetic radiation and projects onto plane on both sides of strip conductor section
    93.
    发明专利
    Integrated circuit has screen for protecting strip conductor section from electromagnetic radiation and projects onto plane on both sides of strip conductor section 未知

    公开(公告)号：DE10127385A1

    公开(公告)日：2002-12-19

    申请号：DE10127385

    申请日：2001-06-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  SCHAFFROTH THILO

    IPC: H01L23/367 ,  H01L23/525 ,  H01L21/768 ,  H01L23/532

    Abstract: An integrated circuit comprises a fuse arranged above a semiconductor substrate and consisting of a strip conductor section (2) running in a first plane above the substrate, a metal strip (12) running in a third plane above the first plane, and a contact element extending between the metal strip and the strip conductor section. A screen (8) is arranged in the second plane to protect the strip conductor section from electromagnetic radiation and projects onto the first plane on both sides of the strip conductor section. The screen is made from the same material as a metal strip section (20) running in a second plane. An Independent claim is also included for a process for the production of an integrated circuit. Preferred Features: The screen running on both sides of the strip conductor section is connected via a bridge arranged in the second plane and consisting of the same material as the metal strip section running in the second plane. The strip conductor section is made from polysilicon. The metal strip is made from aluminum.

    94.
    发明专利
    未知

    公开(公告)号：DE10047251C2

    公开(公告)日：2002-10-17

    申请号：DE10047251

    申请日：2000-09-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT

    IPC: G11C8/10 ,  H03M7/22

    Abstract: Decoder circuit (2) for control of a sample chosen from a number of N output lines (40) dependent on an M-bit address using a switching circuit using two or more parallel pre-decoders (11-13) each of which has a corresponding segment of the M-bit address by activation of a sample decoded from its output lines (a1- a8, b1-b8, c1-c4). At the outputs of each pre-decoder is a device (70), which is activated by a switch on signal (AES) so that the outputs are only coupled to switches (T1-T3) in the control branch when it is switched on.

    95.
    发明专利
    未知

    公开(公告)号：DE10108744A1

    公开(公告)日：2002-09-12

    申请号：DE10108744

    申请日：2001-02-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  CHRYSOLOMINDES ATHANASIA

    IPC: H01L27/02 ,  H01L27/108 ,  G11C11/407 ,  G11C7/06 ,  G11C7/12

    Abstract: The integrated DRAM memory module has sense amplifiers which are each formed, in the integrated module, from a multiplicity of transistor structures that are arranged regularly in cell arrays and include amplification transistors for bit line signal amplification. The amplification transistors lie opposite one another in pairs, are structurally identical, and are arranged equally spaced apart in rows. Voltage equalization transistors ensure voltage equalization between sense amplifier drive signals. The cell array order provides for each row with amplification transistors situated in a structurally identical transistor environment to be interrupted in a predetermined period by voltage equalization transistors. The structure of the voltage equalization transistors in a region of proximity to the adjoining amplification transistors is adapted to the structure thereof, and the voltage equalization transistors are at the same distance from the mutually adjoining amplification transistors as the amplification transistors of the same row are from one another.

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