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    SEMICONDUCTOR ARRANGEMENT PLATE
    1.
    发明专利
    SEMICONDUCTOR ARRANGEMENT PLATE 失效

    公开(公告)号：JP2002008515A

    公开(公告)日：2002-01-11

    申请号：JP2001161394

    申请日：2001-05-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BENEDIX ALEXANDER

    IPC: H01H85/06 ,  H01L23/525 ,  H01H85/055 ,  H01H85/046

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor arrangement plate having an optical fuse in which its component can be repaired through the baking of the fuse. SOLUTION: A semiconductor arrangement plate which has an optical fuse is provided. In this semiconductor, the package material (1) is made of a material which has transparency of the radiation energy that is absorbed by the material of the adjoining fuse (2).

    MEMORY SYSTEM, IN PARTICULAR FOR NETWORK BROADCASTING APPLICATIONS SUCH AS VIDEO/AUDIO APPLICATIONS, AND METHOD FOR OPERATING A MEMORY SYSTEM
    3.
    发明申请
    MEMORY SYSTEM, IN PARTICULAR FOR NETWORK BROADCASTING APPLICATIONS SUCH AS VIDEO/AUDIO APPLICATIONS, AND METHOD FOR OPERATING A MEMORY SYSTEM 审中-公开
    存储系统，特别是对网络广播应用如视频/音频应用，及其操作方法的存储系统

    公开(公告)号：WO2004047364A3

    公开(公告)日：2004-08-12

    申请号：PCT/DE0303576

    申请日：2003-10-28

    Applicant: INFINEON TECHNOLOGIES AG ,  BENEDIX ALEXANDER ,  DANKOWSKI STEFAN ,  DUEREGGER REINHARD ,  RUF WOLFGANG

    Inventor： BENEDIX ALEXANDER ,  DANKOWSKI STEFAN ,  DUEREGGER REINHARD ,  RUF WOLFGANG

    IPC: G11C7/10 ,  H04N5/00 ,  H04N7/173

    CPC classification number: H04N21/2182 ,  G11C7/1018 ,  G11C7/103 ,  H04N21/23116 ,  H04N21/2312 ,  H04N21/2323

    Abstract: The invention relates to a memory system, in particular for network broadcasting applications such as video/audio applications. Said system comprises at least one memory (PM, PM1 to PMi), which is subdivided into several addressable memory units (M1 to Mx), each with its own output (A1 to Ax) for exchanging data. Each input (I1 to Ix) of a matrix switch is connected to a respective output (A1 to Ax) of a different memory unit. The matrix switch is operated in such a way that several of the memory units (M1 to Mx) are connected in sequential order to its outputs (OP1 to OPy), whereby a first sequence of memory units and a second sequence of memory units are connected independently to its outputs. The invention thus provides a memory system, which can service a number of requests to the same server in a deferred manner, whereby the interaction of the individual memory units (M1 to Mx) and the matrix switch (MS) enables a higher data throughput and a short access period.

    Abstract translation: 一种存储系统，特别是对网络的广播应用，例如视频/音频应用中，具有至少一个存储器（PM，PM1至PMI）被划分成多个可寻址存储器单元（M1至MX），其中每个都有自己的输出 （A1至AXE）用于交换数据有。 的输入（I1至ix）的矩阵开关被连接到被连接在不同的存储器单元的各自的输出（A1至斧）。 矩阵开关被操作，使得多个与它的输出（OP1到OPY）按顺序存储单元（M1至MX）的连接，其中的存储器单元中，存储器单元的第二序列的第一序列被独立地连接到其输出端 ， 这提供了一种存储器系统，该系统可以处理数与矩阵开关（MS）请求对同一存储器的时间延迟，其中高数据吞吐量和低存取时间由所述个别存储器单元（M1至MX）的相互作用成为可能的。

    INTEGRATED CIRCUIT WITH A TEMPERATURE SENSOR
    4.
    发明申请
    INTEGRATED CIRCUIT WITH A TEMPERATURE SENSOR 审中-公开
    具有温度传感器集成电路

    公开(公告)号：WO0211147A2

    公开(公告)日：2002-02-07

    申请号：PCT/DE0102802

    申请日：2001-07-24

    Applicant: INFINEON TECHNOLOGIES AG ,  BARTH ROLAND ,  BENEDIX ALEXANDER ,  DUEREGGER REINHARD ,  GROSSE STEPHAN

    Inventor： BARTH ROLAND ,  BENEDIX ALEXANDER ,  DUEREGGER REINHARD ,  GROSSE STEPHAN

    IPC: H01L27/04 ,  G01K7/01 ,  G11C7/04 ,  G11C11/401 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: G01K7/01

    Abstract: A temperature sensor (1) is integrated on the chip together with the integrated circuit. Said temperature sensor supplies a temperature-dependent measuring signal or at least releases a signal when the chip temperature falls below a particular predetermined value. A special circuit device is provided on the chip for this purpose. Said circuit device enables a current flow to be produced through a structure of electrical conductors (2) that is available. The temperature of the integrated circuit is kept above a predetermined minimum temperature with this current flow.

    Abstract translation: 与集成电路一起，温度传感器（1）是集成在芯片上，其提供取决于温度的测量信号，或至少一个发射信号时，芯片的温度低于某一预定值上。 在这种情况下，一种特殊的电路设备存在于芯片上，与通过现有的电导体结构（2）所带来的，与所述集成电路的温度保持在高于预定的最小温度的电流。

    6.
    发明专利
    未知

    公开(公告)号：DE10158564C1

    公开(公告)日：2003-07-17

    申请号：DE10158564

    申请日：2001-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DANKOWSKI STEFAN ,  BENEDIX ALEXANDER ,  DUEREGGER REINHARD ,  RUF WOLFGANG

    IPC: H01L21/768 ,  H01L23/528

    Abstract: The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1'; B1''), which is composed of a plurality of interconnect sections (A11-A16; A11'-A16'; A11''-A14'') lying in a first and a second interconnect plane (M0, M1); and a second interconnect (B2; B2'; B2''), which runs adjacent to the first interconnect (B1; B1'; B1'') and which is composed of a plurality of interconnect sections (A21-A25; A21'-A25'; A21''-A23'') lying in the first and second interconnect planes (M0, M1); the first and second interconnects (B1; B1'; B1''; B2; B2'; B2'') being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A12, A14, A16; A12', A14', A16'; A12'', A14'') of the first interconnect (B1; B1'; B1'') which lie in the first interconnect plane (M0) run at least in sections beside the interconnect sections (A22, A24; A22'; A24'; A21'', A23'') of the second interconnect (B2; B2'; B2'') which lie in the second interconnection plane (M1), and that the interconnect sections (A11, A13, A

    7.
    发明专利
    未知

    公开(公告)号：DE10146931A1

    公开(公告)日：2003-04-30

    申请号：DE10146931

    申请日：2001-09-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUF WOLFGANG ,  BENEDIX ALEXANDER ,  DUEREGGER REINHARD

    IPC: G11C29/00

    Abstract: A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.

    Operating computer system involves comparing code processing efficiency assessments to select more efficient configuration parameter set and configuring components accordingly
    10.
    发明专利
    Operating computer system involves comparing code processing efficiency assessments to select more efficient configuration parameter set and configuring components accordingly 未知

    公开(公告)号：DE10114777A1

    公开(公告)日：2002-10-10

    申请号：DE10114777

    申请日：2001-03-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BENEDIX ALEXANDER ,  BRAUN GEORG ,  KLEHN BERND

    IPC: G06F9/445 ,  G06F15/177

    Abstract: The method involves selecting a first configuration parameter set, configuring system components accordingly, processing a first program code, determining a first assessment of processing efficiency, selecting a second parameter set, processing a second program code, determining a second efficiency assessment, comparing the assessments, selecting the more efficient parameter set and configuring system components accordingly. The method involves providing a computer system (5) with functionally configurable components (10), selecting a first configuration parameter set (15), configuring the system components accordingly, processing a first program code (20), determining a first assessment of processing efficiency, selecting a second parameter set (30), processing a second program code (35), determining a second efficiency assessment, comparing the assessments, selecting the more efficient parameter set and configuring accordingly. Independent claims are also included for the following: a computer system and a computer program product.

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